MBX Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 mbx_smoke mbx_smoke 1.633m 19.034ms 2 2 100.00
V1 csr_hw_reset mbx_csr_hw_reset 5.000s 14.125us 5 5 100.00
V1 csr_rw mbx_csr_rw 5.000s 13.892us 20 20 100.00
V1 csr_bit_bash mbx_csr_bit_bash 6.000s 409.361us 5 5 100.00
V1 csr_aliasing mbx_csr_aliasing 5.000s 14.119us 5 5 100.00
V1 csr_mem_rw_with_rand_reset mbx_csr_mem_rw_with_rand_reset 5.000s 2.792us 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr mbx_csr_rw 5.000s 13.892us 20 20 100.00
mbx_csr_aliasing 5.000s 14.119us 5 5 100.00
V1 TOTAL 37 57 64.91
V2 mbx_stress mbx_stress 2.567m 8.972ms 2 2 100.00
mbx_stress_zero_delays 2.283m 9.025ms 2 2 100.00
V2 mbx_imbx_oob mbx_imbx_oob 1.183m 11.917ms 2 2 100.00
V2 alert_test mbx_alert_test 38.000s 50.535us 50 50 100.00
V2 tl_d_oob_addr_access mbx_tl_errors 5.000s 927.114ns 0 20 0.00
V2 tl_d_illegal_access mbx_tl_errors 5.000s 927.114ns 0 20 0.00
V2 tl_d_outstanding_access mbx_csr_hw_reset 5.000s 14.125us 5 5 100.00
mbx_csr_rw 5.000s 13.892us 20 20 100.00
mbx_csr_aliasing 5.000s 14.119us 5 5 100.00
mbx_same_csr_outstanding 5.000s 21.486us 20 20 100.00
V2 tl_d_partial_access mbx_csr_hw_reset 5.000s 14.125us 5 5 100.00
mbx_csr_rw 5.000s 13.892us 20 20 100.00
mbx_csr_aliasing 5.000s 14.119us 5 5 100.00
mbx_same_csr_outstanding 5.000s 21.486us 20 20 100.00
V2 TOTAL 76 96 79.17
V2S tl_intg_err mbx_sec_cm 38.000s 12.723us 5 5 100.00
mbx_tl_intg_err 5.000s 4.203us 0 20 0.00
V2S TOTAL 5 25 20.00
TOTAL 118 178 66.29

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
89.37 96.82 92.25 96.64 80.03 78.94 -- 98.54 65.23

Failure Buckets