OTBN Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: `2995ba4`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	52.000s	44.945us	1	1	100.00
V1	single_binary	otbn_single	6.833m	2.369ms	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	24.697us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	19.305us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	406.026us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	22.982us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	14.000s	141.101us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	19.305us	20	20	100.00
		otbn_csr_aliasing	7.000s	22.982us	5	5	100.00
V1	mem_walk	otbn_mem_walk	38.000s	7.675ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	15.000s	245.297us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	54.000s	119.258us	10	10	100.00
V2	multi_error	otbn_multi_err	53.000s	482.795us	1	1	100.00
V2	back_to_back	otbn_multi	1.567m	1.161ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.733m	465.493us	10	10	100.00
V2	lc_escalation	otbn_escalate	27.000s	86.909us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	13.000s	62.635us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	27.000s	74.725us	10	10	100.00
V2	alert_test	otbn_alert_test	12.000s	31.079us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	31.173us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	161.052us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	161.052us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	24.697us	5	5	100.00
		otbn_csr_rw	9.000s	19.305us	20	20	100.00
		otbn_csr_aliasing	7.000s	22.982us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	21.648us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	24.697us	5	5	100.00
		otbn_csr_rw	9.000s	19.305us	20	20	100.00
		otbn_csr_aliasing	7.000s	22.982us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	21.648us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	27.000s	63.434us	10	10	100.00
		otbn_dmem_err	25.000s	90.151us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	205.002us	5	5	100.00
		otbn_controller_ispr_rdata_err	16.000s	242.362us	5	5	100.00
		otbn_mac_bignum_acc_err	15.000s	64.833us	5	5	100.00
		otbn_urnd_err	9.000s	19.897us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	14.464us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	23.987us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	37.067us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
		otbn_tl_intg_err	1.317m	429.912us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	44.000s	235.244us	19	20	95.00
V2S	prim_fsm_check	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	52.000s	44.945us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	25.000s	90.151us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	27.000s	63.434us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.317m	429.912us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	27.000s	86.909us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	27.000s	63.434us	10	10	100.00
		otbn_dmem_err	25.000s	90.151us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	62.635us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	14.464us	5	5	100.00
		otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	6.833m	2.369ms	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	27.000s	63.434us	10	10	100.00
		otbn_dmem_err	25.000s	90.151us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	62.635us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	14.464us	5	5	100.00
		otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	27.000s	86.909us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	27.000s	63.434us	10	10	100.00
		otbn_dmem_err	25.000s	90.151us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	62.635us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	14.464us	5	5	100.00
		otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	6.833m	2.369ms	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	17.000s	41.097us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	13.000s	22.069us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.017m	167.147us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.017m	167.147us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	24.795us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	66.572us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.067m	836.730us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.067m	836.730us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	18.234us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	6.833m	2.369ms	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	6.833m	2.369ms	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	6.833m	2.369ms	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.567m	1.161ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	6.833m	2.369ms	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	6.833m	2.369ms	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	17.741us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	6.833m	2.369ms	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.483m	2.094ms	2	5	40.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	6.200m	2.156ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			568	585	97.09

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.12	99.64	95.95	99.72	93.17	93.90	97.44	97.85	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 3.otbn_stress_all_with_rand_reset.51010267168389686373423655686899028690110099603079409644965359069677401542296
    Line 163, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 877022458 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 877022458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.otbn_stress_all_with_rand_reset.62206052484008897492748175414541698824686808647560412482775294522948161695712
    Line 344, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 638151099 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 638151099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

1.otbn_sec_cm.55705063129516534854168022978372644012105200595384076553548581616264318003829
Line 119, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 182836538 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 182836538 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @ 182836538 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @ 182836538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_cm.96788833625160330782630780819738959186571453833076225284367209074985682512389
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 1781123 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 1781123 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @   1781123 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @   1781123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.37155397281400528193584714847558223553526737978599000073061130150380147519913
    Line 150, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  42551415 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  42551415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.otbn_stress_all_with_rand_reset.10770880705975514092129786047694450812669603218631143069191592534823549058664
    Line 208, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 470882507 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 470882507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 1.otbn_stress_all_with_rand_reset.49312351237491502769222506586859200280663773493791035093201373247377468715185
    Line 141, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   7968696 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @   7968696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.otbn_stress_all_with_rand_reset.98177348091244040995554359358691674898814805068104715197341211338808083298684
    Line 410, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3121526352 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 3121526352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_escalate has 2 failures.

47.otbn_escalate.81995836554834548995787428812452419609219369793408217374589959419014690961543
Line 114, in log /nightly/runs/scratch/master/otbn-sim-xcelium/47.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 121221936 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 121221936 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 121221936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

55.otbn_escalate.22641453495406444135055848270606739555065553349255505140862753036451796449588
Line 115, in log /nightly/runs/scratch/master/otbn-sim-xcelium/55.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 118938978 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 118938978 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 118938978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 7.otbn_passthru_mem_tl_intg_err.107476923252847227903989074841339462141400047380875478254943615631755057762933
    Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/7.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 183958384 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @ 183958384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 10.otbn_escalate.31405571839341310950460867698433256401476556479609452604160550010829958651517
    Line 101, in log /nightly/runs/scratch/master/otbn-sim-xcelium/10.otbn_escalate/latest/run.log
```
  UVM_ERROR @   2853160 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   2853160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_single has 1 failures.
  - 35.otbn_single.76723955353638009471330879579123161526278511629988551232004424504575122900283
    Line 99, in log /nightly/runs/scratch/master/otbn-sim-xcelium/35.otbn_single/latest/run.log
```
  UVM_FATAL @  21780248 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  21780248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```