ROM_CTRL/32KB Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.650s	180.620us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.380s	184.086us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	8.230s	174.885us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.000s	1.804ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.460s	540.025us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.750s	146.454us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	8.230s	174.885us	20	20	100.00
		rom_ctrl_csr_aliasing	8.460s	540.025us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.780s	172.690us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.290s	2.496ms	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.210s	334.088us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	26.190s	10.173ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.720s	1.042ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.020s	164.221us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.330s	219.314us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.330s	219.314us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.380s	184.086us	5	5	100.00
		rom_ctrl_csr_rw	8.230s	174.885us	20	20	100.00
		rom_ctrl_csr_aliasing	8.460s	540.025us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.570s	169.537us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.380s	184.086us	5	5	100.00
		rom_ctrl_csr_rw	8.230s	174.885us	20	20	100.00
		rom_ctrl_csr_aliasing	8.460s	540.025us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.570s	169.537us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.916m	3.150ms	16	20	80.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	28.730s	14.298ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.381m	1.024ms	5	5	100.00
		rom_ctrl_tl_intg_err	58.770s	1.145ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.381m	1.024ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.381m	1.024ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.916m	3.150ms	16	20	80.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.916m	3.150ms	16	20	80.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.916m	3.150ms	16	20	80.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.916m	3.150ms	16	20	80.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.916m	3.150ms	16	20	80.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.381m	1.024ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.381m	1.024ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.650s	180.620us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.650s	180.620us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.650s	180.620us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	58.770s	1.145ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.916m	3.150ms	16	20	80.00
		rom_ctrl_kmac_err_chk	9.720s	1.042ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.916m	3.150ms	16	20	80.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.916m	3.150ms	16	20	80.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.916m	3.150ms	16	20	80.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	28.730s	14.298ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.381m	1.024ms	5	5	100.00
V2S		TOTAL			61	65	93.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	7.817m	18.879ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			262	266	98.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.73	99.41	100.00	100.00	100.00	98.98	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 4 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.

    • 2.rom_ctrl_corrupt_sig_fatal_chk.53418986663119467088119759051940551187175433523582720989815279772791900816448
      Line 96, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 6250873971 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 6250873971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.rom_ctrl_corrupt_sig_fatal_chk.47187504995183751039555766465057108510259323560635918595900479372176936894484
      Line 78, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 762626103 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 762626103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.