RV_TIMER Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.120s	12.117us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.920s	46.403us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.180s	13.727us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.110s	429.803us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.210s	34.357us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.640s	87.000us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.180s	13.727us	20	20	100.00
		rv_timer_csr_aliasing	2.210s	34.357us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	14.910s	29.887ms	20	20	100.00
V2	disabled	rv_timer_disabled	4.090s	1.440ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	11.518m	511.743ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	11.518m	511.743ms	10	10	100.00
V2	stress	rv_timer_stress_all	9.520s	6.411ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.300s	40.582us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.100s	15.122us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.610s	293.248us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.610s	293.248us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.920s	46.403us	5	5	100.00
		rv_timer_csr_rw	2.180s	13.727us	20	20	100.00
		rv_timer_csr_aliasing	2.210s	34.357us	5	5	100.00
		rv_timer_same_csr_outstanding	2.380s	30.574us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.920s	46.403us	5	5	100.00
		rv_timer_csr_rw	2.180s	13.727us	20	20	100.00
		rv_timer_csr_aliasing	2.210s	34.357us	5	5	100.00
		rv_timer_same_csr_outstanding	2.380s	30.574us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.320s	211.999us	5	5	100.00
		rv_timer_tl_intg_err	3.070s	126.790us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.070s	126.790us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.069m	13.462ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	2.120s	17.932us	10	10	100.00
		rv_timer_max	2.040s	66.952us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.44	100.00	100.00	78.66	--	100.00	100.00	100.00