SPI_DEVICE/1R1W Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.908m	56.889ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.260s	44.582us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.500s	114.559us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.720s	10.013ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.920s	1.602ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.100s	153.522us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.500s	114.559us	20	20	100.00
		spi_device_csr_aliasing	16.920s	1.602ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.910s	130.838us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.180s	280.492us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.400s	94.396us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.270s	996.007ns	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.850s	9.034us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	10.250s	916.527us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.250s	916.527us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.360s	9.603ms	50	50	100.00
		spi_device_tpm_sts_read	2.690s	117.494us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	42.580s	7.314ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.330s	7.274ms	50	50	100.00
		spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	53.550s	15.076ms	50	50	100.00
		spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	53.550s	15.076ms	50	50	100.00
		spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	37.110s	40.478ms	50	50	100.00
		spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	37.110s	40.478ms	50	50	100.00
		spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	37.110s	40.478ms	50	50	100.00
		spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	37.110s	40.478ms	50	50	100.00
		spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	37.110s	40.478ms	50	50	100.00
		spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.046m	166.958ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.247m	8.117ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.247m	8.117ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.247m	8.117ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.667m	8.470ms	50	50	100.00
		spi_device_read_buffer_direct	17.300s	3.628ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.247m	8.117ms	50	50	100.00
		spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.647m	438.918ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.650s	5.761ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.650s	5.761ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.908m	56.889ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.264m	249.766ms	49	50	98.00
V2	stress_all	spi_device_stress_all	11.847m	155.520ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.340s	15.426us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.250s	50.626us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.270s	230.831us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.270s	230.831us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.260s	44.582us	5	5	100.00
		spi_device_csr_rw	3.500s	114.559us	20	20	100.00
		spi_device_csr_aliasing	16.920s	1.602ms	5	5	100.00
		spi_device_same_csr_outstanding	4.370s	166.760us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.260s	44.582us	5	5	100.00
		spi_device_csr_rw	3.500s	114.559us	20	20	100.00
		spi_device_csr_aliasing	16.920s	1.602ms	5	5	100.00
		spi_device_same_csr_outstanding	4.370s	166.760us	20	20	100.00
V2		TOTAL			939	961	97.71
V2S	tl_intg_err	spi_device_sec_cm	2.360s	81.943us	5	5	100.00
		spi_device_tl_intg_err	19.540s	3.800ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.540s	3.800ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.083m	153.172ms	50	50	100.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.80	99.11	96.50	71.19	89.36	98.39	95.76	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.114010728480550539096703777067670026833281261895225358933511882401269431293051
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   9135685 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[26])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   9135685 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   9135685 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[922])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.98265847885248834004787872484757482104962815706400466720941860213673129672641
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1188954 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[84])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1188954 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1188954 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[980])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.66990180351426394511982162431461705253601064601415124642785309050168208782350
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   6319662 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcc1b5 [11001100000110110101] vs 0x0 [0])
  UVM_ERROR @   6345662 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc8aa29 [110010001010101000101001] vs 0x0 [0])
  UVM_ERROR @   6359662 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x500f98 [10100000000111110011000] vs 0x0 [0])
  UVM_ERROR @   6378662 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x20a015 [1000001010000000010101] vs 0x0 [0])
  UVM_ERROR @   6382662 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xca517b [110010100101000101111011] vs 0x0 [0])

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_and_tpm_min_idle has 1 failures.
  - 24.spi_device_flash_and_tpm_min_idle.66694546571844459286663515671907881881314820016937072116455487822171075575684
    Line 125, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```