SPI_HOST Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.933m	22.469ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	37.626us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	28.463us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	310.399us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	229.749us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	19.928us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	28.463us	20	20	100.00
		spi_host_csr_aliasing	4.000s	229.749us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	31.356us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	73.561us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	6.000s	256.736us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	27.000s	1.730ms	50	50	100.00
		spi_host_error_cmd	5.000s	31.399us	50	50	100.00
		spi_host_event	16.283m	133.023ms	50	50	100.00
V2	clock_rate	spi_host_speed	15.000s	542.031us	50	50	100.00
V2	speed	spi_host_speed	15.000s	542.031us	50	50	100.00
V2	chip_select_timing	spi_host_speed	15.000s	542.031us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	2.250m	10.016ms	48	50	96.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	109.526us	50	50	100.00
V2	cpol_cpha	spi_host_speed	15.000s	542.031us	50	50	100.00
V2	full_cycle	spi_host_speed	15.000s	542.031us	50	50	100.00
V2	duplex	spi_host_smoke	1.933m	22.469ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.933m	22.469ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.583m	4.007ms	50	50	100.00
V2	spien	spi_host_spien	3.983m	13.854ms	50	50	100.00
V2	stall	spi_host_status_stall	16.533m	1.000s	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	31.000s	1.575ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	27.000s	1.730ms	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	45.497us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	15.180us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	88.560us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	88.560us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	37.626us	5	5	100.00
		spi_host_csr_rw	5.000s	28.463us	20	20	100.00
		spi_host_csr_aliasing	4.000s	229.749us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	31.376us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	37.626us	5	5	100.00
		spi_host_csr_rw	5.000s	28.463us	20	20	100.00
		spi_host_csr_aliasing	4.000s	229.749us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	31.376us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	187.694us	20	20	100.00
		spi_host_sec_cm	5.000s	281.000us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	187.694us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	14.567m	100.020ms	8	10	80.00
		TOTAL			834	840	99.29

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.20	96.78	93.27	98.69	94.36	73.07	100.00	97.29	90.42

Failure Buckets

UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 2 failures:

Test spi_host_sw_reset has 2 failures.

1.spi_host_sw_reset.75867100012909608733813421993943842510612695095820189925502934948259772756042
Line 204, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10015975282 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxempty (addr=0x326534d4, Comparison=CompareOpEq, exp_data=0x0, call_count=35
  UVM_INFO @ 10015975282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.spi_host_sw_reset.54947989052040713862151570075479210664572097678475280334610008188747871289576
Line 162, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10009656898 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxempty (addr=0x84d47a94, Comparison=CompareOpEq, exp_data=0x0, call_count=25
  UVM_INFO @ 10009656898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 9.spi_host_upper_range_clkdiv.27610547772059720261611232829436679065353448106275708986193094495596933648951
    Line 124, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 37.spi_host_status_stall.76987385562354180639820971836736507069028088870736754105353180641140787290191
    Line 1347, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/37.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

5.spi_host_status_stall.60580348584613322394100309080079215482966812699604862493458363821733803464809
Line 1507, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 81143968072 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 81143968072 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=81143968000 ps
  UVM_INFO @ 81143968072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 6.spi_host_upper_range_clkdiv.25178707742804924324730229242823160680367478173694995648877314869347792665272
    Line 141, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100019790403 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0xa14de254, Comparison=CompareOpEq, exp_data=0x0, call_count=15
  UVM_INFO @ 100019790403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```