SRAM_CTRL/MAIN Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.813m	1.012ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.170s	21.730us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.210s	31.136us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.970s	774.165us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.270s	24.693us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.140s	1.409ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.210s	31.136us	20	20	100.00
		sram_ctrl_csr_aliasing	2.270s	24.693us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.938m	14.397ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.234m	100.491ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	24.452m	47.820ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.876m	11.178ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	43.076m	245.501ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.488m	150.155ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.212m	30.938ms	50	50	100.00
V2	executable	sram_ctrl_executable	16.889m	24.034ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.597m	530.182us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.384m	109.308ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.850m	1.599ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.710m	1.565ms	50	50	100.00
		sram_ctrl_throughput_w_readback	2.035m	1.759ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	17.423m	96.697ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.870s	2.577ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.143h	1.497s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.210s	28.145us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.430s	621.917us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.430s	621.917us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.170s	21.730us	5	5	100.00
		sram_ctrl_csr_rw	2.210s	31.136us	20	20	100.00
		sram_ctrl_csr_aliasing	2.270s	24.693us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.310s	25.434us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.170s	21.730us	5	5	100.00
		sram_ctrl_csr_rw	2.210s	31.136us	20	20	100.00
		sram_ctrl_csr_aliasing	2.270s	24.693us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.310s	25.434us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.119m	7.415ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.330s	6.109us	0	5	0.00
		sram_ctrl_tl_intg_err	4.490s	674.404us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.330s	6.109us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.490s	674.404us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	17.423m	96.697ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	17.423m	96.697ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.210s	31.136us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	16.889m	24.034ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	16.889m	24.034ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	16.889m	24.034ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.212m	30.938ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.950s	3.998ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.119m	7.415ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	12.880s	9.397ms	36	50	72.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.813m	1.012ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.813m	1.012ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	16.889m	24.034ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.330s	6.109us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.212m	30.938ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.330s	6.109us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.330s	6.109us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.813m	1.012ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.330s	6.109us	0	5	0.00
V2S		TOTAL			120	145	82.76
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.524m	3.195ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1165	1190	97.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.11	93.01	85.18	100.00	98.03	98.61	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 14 failures:
  • Test sram_ctrl_readback_err has 14 failures.

    • 0.sram_ctrl_readback_err.3532388007112091790841058673467115682004968904430185565580619171338640396264
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2436332841 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x35) != exp (0x34)
        UVM_INFO @ 2436332841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_readback_err.6920545225238109149639070068838145846723357801485810931924897791697191637816
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2736969490 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4f) != exp (0x4c)
        UVM_INFO @ 2736969490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 12 more failures.

• Offending 'reqfifo_rvalid' has 6 failures:
  • Test sram_ctrl_mubi_enc_err has 6 failures.

    • 0.sram_ctrl_mubi_enc_err.6732108227520522975446983572537104986709617422639852263917559580490746588577
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 669832991 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 669832991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_mubi_enc_err.24506001837010328027126307429975842628758240565761563411115194101171125910764
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1870426106 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1870426106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:
  • Test sram_ctrl_sec_cm has 3 failures.

    • 1.sram_ctrl_sec_cm.88070523528441012533080180890789516244685150322431764030735865998714365813194
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  48226821 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  48226821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.76119963139280843419435603262401219502445013564669210647131730000269800911645
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3023903 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3023903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending 'pend_req[d2h.d_source].pend' has 2 failures:
  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.10717650713553256674336856154671041646565926237001444843311715929928754894038
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   4769263 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   4769263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.52664501275697214726466875612228229787263287802786891910882818098829550553389
      Line 102, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   6108624 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   6108624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---