SRAM_CTRL/RET Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.717m	2.584ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.220s	13.123us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.080s	31.632us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.880s	323.744us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.000s	28.896us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.780s	62.133us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.080s	31.632us	20	20	100.00
		sram_ctrl_csr_aliasing	2.000s	28.896us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.240s	2.633ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.690s	188.728us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	19.921m	32.225ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.694m	8.208ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.421m	31.540ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.444m	15.411ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.060s	1.861ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.933m	18.669ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.852m	2.457ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.520m	155.480ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.002m	161.876us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.830m	146.296us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.723m	1.155ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	21.270m	113.291ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.260s	81.716us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.221h	153.831ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.200s	39.157us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.610s	196.952us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.610s	196.952us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.220s	13.123us	5	5	100.00
		sram_ctrl_csr_rw	2.080s	31.632us	20	20	100.00
		sram_ctrl_csr_aliasing	2.000s	28.896us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.230s	20.263us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.220s	13.123us	5	5	100.00
		sram_ctrl_csr_rw	2.080s	31.632us	20	20	100.00
		sram_ctrl_csr_aliasing	2.000s	28.896us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.230s	20.263us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.960s	7.868ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.150s	6.848us	0	5	0.00
		sram_ctrl_tl_intg_err	3.690s	772.691us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.150s	6.848us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.690s	772.691us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	21.270m	113.291ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	21.270m	113.291ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.080s	31.632us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.933m	18.669ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.933m	18.669ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.933m	18.669ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.060s	1.861ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.590s	371.922us	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.960s	7.868ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.610s	105.794us	35	50	70.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.717m	2.584ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.717m	2.584ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.933m	18.669ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.150s	6.848us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.060s	1.861ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.150s	6.848us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.150s	6.848us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.717m	2.584ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.150s	6.848us	0	5	0.00
V2S		TOTAL			119	145	82.07
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.540m	1.956ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1161	1190	97.56

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	99.07	93.01	85.10	100.00	97.99	98.60	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 15 failures:

  • Test sram_ctrl_readback_err has 15 failures.

    • 0.sram_ctrl_readback_err.24069794546823760652116315464312238194825638385958980589035319734168513850727
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 433762155 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x51) != exp (0x78)
        UVM_INFO @ 433762155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_readback_err.70895299054098047318660579861909962375009030249533964181997137723871308964522
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  25059373 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x53) != exp (0x56)
        UVM_INFO @  25059373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 13 more failures.

• Offending 'reqfifo_rvalid' has 6 failures:

  • Test sram_ctrl_mubi_enc_err has 6 failures.

    • 7.sram_ctrl_mubi_enc_err.78403358371537696801597013597683110990955937194391306559796176441478974419863
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  25812969 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  25812969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.sram_ctrl_mubi_enc_err.97610309376684940011827863857440130418759166853692890602763327900707740021608
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  55587369 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  55587369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.88557603112418238825995412619916085273081736756714831836469189001109310677727
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7020244 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7020244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.23560501013343880238596321022743381377579035169894909874502041608509283077249
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6848400 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6848400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.110663175881105123104365289080014511682249774701370684947331542417821794619795
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @    939193 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @    939193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.33378646640351186759531865779226195515229753417688972739457701406830666839458
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   4084245 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   4084245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 6.sram_ctrl_csr_mem_rw_with_rand_reset.13132148820830541958641324913403650022861733868607595164113896342922072542258
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  98687441 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
        UVM_INFO @  98687441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 10.sram_ctrl_csr_mem_rw_with_rand_reset.92577083942072401272072343918698335840766397027140153699441802340714617025361
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  22559756 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  22559756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 19.sram_ctrl_stress_all_with_rand_reset.81989018669505453311436346662902572868583377797094066500888919883798190303491
      Line 219, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16670332486 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 16670332486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---