AES/MASKED Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: `2211fb0`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	61.707us	1	1	100.00
V1	smoke	aes_smoke	18.000s	1.484ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	58.276us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	70.558us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.979ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	89.603us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	68.380us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	70.558us	20	20	100.00
		aes_csr_aliasing	6.000s	89.603us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	18.000s	1.484ms	50	50	100.00
		aes_config_error	17.000s	827.946us	50	50	100.00
		aes_stress	1.400m	4.969ms	50	50	100.00
V2	key_length	aes_smoke	18.000s	1.484ms	50	50	100.00
		aes_config_error	17.000s	827.946us	50	50	100.00
		aes_stress	1.400m	4.969ms	50	50	100.00
V2	back2back	aes_stress	1.400m	4.969ms	50	50	100.00
		aes_b2b	25.000s	438.725us	50	50	100.00
V2	backpressure	aes_stress	1.400m	4.969ms	50	50	100.00
V2	multi_message	aes_smoke	18.000s	1.484ms	50	50	100.00
		aes_config_error	17.000s	827.946us	50	50	100.00
		aes_stress	1.400m	4.969ms	50	50	100.00
		aes_alert_reset	1.967m	7.313ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	282.802us	50	50	100.00
		aes_config_error	17.000s	827.946us	50	50	100.00
		aes_alert_reset	1.967m	7.313ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.383m	5.037ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	672.592us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.967m	7.313ms	50	50	100.00
V2	stress	aes_stress	1.400m	4.969ms	50	50	100.00
V2	sideload	aes_stress	1.400m	4.969ms	50	50	100.00
		aes_sideload	19.000s	811.871us	50	50	100.00
V2	deinitialization	aes_deinit	25.000s	5.257ms	50	50	100.00
V2	stress_all	aes_stress_all	12.233m	38.028ms	9	10	90.00
V2	alert_test	aes_alert_test	6.000s	127.662us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	399.724us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	399.724us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	58.276us	5	5	100.00
		aes_csr_rw	6.000s	70.558us	20	20	100.00
		aes_csr_aliasing	6.000s	89.603us	5	5	100.00
		aes_same_csr_outstanding	6.000s	246.660us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	58.276us	5	5	100.00
		aes_csr_rw	6.000s	70.558us	20	20	100.00
		aes_csr_aliasing	6.000s	89.603us	5	5	100.00
		aes_same_csr_outstanding	6.000s	246.660us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	15.000s	651.503us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	540.689us	50	50	100.00
		aes_control_fi	46.000s	10.004ms	278	300	92.67
		aes_cipher_fi	41.000s	10.006ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	68.495us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	68.495us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	68.495us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	68.495us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	587.823us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	20.000s	9.678ms	5	5	100.00
		aes_tl_intg_err	9.000s	1.072ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	1.072ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.967m	7.313ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	68.495us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	1.484ms	50	50	100.00
		aes_stress	1.400m	4.969ms	50	50	100.00
		aes_alert_reset	1.967m	7.313ms	50	50	100.00
		aes_core_fi	53.000s	10.148ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	68.495us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	85.246us	50	50	100.00
		aes_stress	1.400m	4.969ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.400m	4.969ms	50	50	100.00
		aes_sideload	19.000s	811.871us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	85.246us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	85.246us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	85.246us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	85.246us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	85.246us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.400m	4.969ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.400m	4.969ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	540.689us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	540.689us	50	50	100.00
		aes_control_fi	46.000s	10.004ms	278	300	92.67
		aes_cipher_fi	41.000s	10.006ms	340	350	97.14
		aes_ctr_fi	6.000s	89.852us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	540.689us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	540.689us	50	50	100.00
		aes_control_fi	46.000s	10.004ms	278	300	92.67
		aes_cipher_fi	41.000s	10.006ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	41.000s	10.006ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	540.689us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	540.689us	50	50	100.00
		aes_control_fi	46.000s	10.004ms	278	300	92.67
		aes_ctr_fi	6.000s	89.852us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	540.689us	50	50	100.00
		aes_control_fi	46.000s	10.004ms	278	300	92.67
		aes_cipher_fi	41.000s	10.006ms	340	350	97.14
		aes_ctr_fi	6.000s	89.852us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.967m	7.313ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	540.689us	50	50	100.00
		aes_control_fi	46.000s	10.004ms	278	300	92.67
		aes_cipher_fi	41.000s	10.006ms	340	350	97.14
		aes_ctr_fi	6.000s	89.852us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	540.689us	50	50	100.00
		aes_control_fi	46.000s	10.004ms	278	300	92.67
		aes_cipher_fi	41.000s	10.006ms	340	350	97.14
		aes_ctr_fi	6.000s	89.852us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	540.689us	50	50	100.00
		aes_control_fi	46.000s	10.004ms	278	300	92.67
		aes_ctr_fi	6.000s	89.852us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	540.689us	50	50	100.00
		aes_control_fi	46.000s	10.004ms	278	300	92.67
		aes_cipher_fi	41.000s	10.006ms	340	350	97.14
V2S		TOTAL			950	985	96.45
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	41.000s	813.016us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1556	1602	97.13

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.43	98.65	96.59	99.47	95.55	98.07	100.00	98.96	98.79

Failure Buckets

Job timed out after * minutes has 13 failures:
- Test aes_control_fi has 13 failures.
  - 8.aes_control_fi.65079792484640350263945280943448026931493096099429300800237795287164760861043
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 69.aes_control_fi.76022376080700488012584559554961998548721671459041175408336425556944931684518
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/69.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 30.aes_cipher_fi.94780105183461590965038572514168242392265567195514307091966514541876105091176
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011585779 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011585779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 44.aes_cipher_fi.26438271037608621078810081204787632539529482580645726462265002882356079917587
    Line 136, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10109901131 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10109901131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 29.aes_control_fi.45133051718469844350557789345872927565281978871751831294303470974343182059941
    Line 133, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10076033886 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10076033886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 40.aes_control_fi.14906492038458006525126678503270379261517334211108350541818656737837180996749
    Line 145, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003021352 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003021352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.98609707603497123294035680976732481850595727871699638131216286250228981743765
Line 915, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 813015569 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 813015569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.11178833398263284456907361093583969707348374814171105795894489781049752788507
Line 258, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1193241608 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1193241608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 4 failures:
- Test aes_stress_all_with_rand_reset has 4 failures.
  - 3.aes_stress_all_with_rand_reset.49574697056965687443837147208300952619594552833041988376571539531235540015342
    Line 767, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 588272669 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 588272669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.58578625454268928501095733756798929429589602162258064884713102519037674995802
    Line 157, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 469883464 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 469883464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 16.aes_core_fi.55083047338864252676433818383057025237577827927542882565383012867948023549088
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10147949617 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10147949617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 39.aes_core_fi.72005819547748055465406803781584082998985844570534188068403574623799814974589
    Line 145, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/39.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013970698 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013970698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=37) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 3.aes_stress_all.114170452489653055962157854717528324232026184054960318745507434473618661984509
    Line 183620, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 10610005084 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xae2e6584, Comparison=CompareOpEq, exp_data=0x1, call_count=37)
  UVM_INFO @ 10610005084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block.status reset value: * has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.24259507408531068057196189783835116361717403333434458107034771936517923972725
    Line 212, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  19686167 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (64 [0x40] vs 0 [0x0]) Regname: aes_reg_block.status reset value: 0x0
  UVM_INFO @  19686167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```