AES/UNMASKED Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: `2211fb0`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	75.572us	1	1	100.00
V1	smoke	aes_smoke	6.000s	389.714us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	104.832us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	54.792us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.028ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	226.166us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	69.794us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	54.792us	20	20	100.00
		aes_csr_aliasing	7.000s	226.166us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	389.714us	50	50	100.00
		aes_config_error	8.000s	232.933us	50	50	100.00
		aes_stress	7.000s	207.667us	50	50	100.00
V2	key_length	aes_smoke	6.000s	389.714us	50	50	100.00
		aes_config_error	8.000s	232.933us	50	50	100.00
		aes_stress	7.000s	207.667us	50	50	100.00
V2	back2back	aes_stress	7.000s	207.667us	50	50	100.00
		aes_b2b	9.000s	331.113us	50	50	100.00
V2	backpressure	aes_stress	7.000s	207.667us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	389.714us	50	50	100.00
		aes_config_error	8.000s	232.933us	50	50	100.00
		aes_stress	7.000s	207.667us	50	50	100.00
		aes_alert_reset	6.000s	192.103us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	57.798us	50	50	100.00
		aes_config_error	8.000s	232.933us	50	50	100.00
		aes_alert_reset	6.000s	192.103us	50	50	100.00
V2	trigger_clear_test	aes_clear	8.000s	1.305ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	202.835us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	192.103us	50	50	100.00
V2	stress	aes_stress	7.000s	207.667us	50	50	100.00
V2	sideload	aes_stress	7.000s	207.667us	50	50	100.00
		aes_sideload	8.000s	197.850us	50	50	100.00
V2	deinitialization	aes_deinit	7.000s	799.923us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	10.942ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	119.236us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	68.167us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	68.167us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	104.832us	5	5	100.00
		aes_csr_rw	6.000s	54.792us	20	20	100.00
		aes_csr_aliasing	7.000s	226.166us	5	5	100.00
		aes_same_csr_outstanding	6.000s	133.779us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	104.832us	5	5	100.00
		aes_csr_rw	6.000s	54.792us	20	20	100.00
		aes_csr_aliasing	7.000s	226.166us	5	5	100.00
		aes_same_csr_outstanding	6.000s	133.779us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	7.000s	285.602us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	682.724us	48	50	96.00
		aes_control_fi	30.000s	10.010ms	285	300	95.00
		aes_cipher_fi	31.000s	10.003ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	129.690us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	129.690us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	129.690us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	129.690us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	180.938us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	515.537us	5	5	100.00
		aes_tl_intg_err	10.000s	1.053ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	1.053ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	192.103us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	129.690us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	389.714us	50	50	100.00
		aes_stress	7.000s	207.667us	50	50	100.00
		aes_alert_reset	6.000s	192.103us	50	50	100.00
		aes_core_fi	28.000s	10.022ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	129.690us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	60.747us	50	50	100.00
		aes_stress	7.000s	207.667us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	207.667us	50	50	100.00
		aes_sideload	8.000s	197.850us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	60.747us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	60.747us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	60.747us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	60.747us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	60.747us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	207.667us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	207.667us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	682.724us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	682.724us	48	50	96.00
		aes_control_fi	30.000s	10.010ms	285	300	95.00
		aes_cipher_fi	31.000s	10.003ms	324	350	92.57
		aes_ctr_fi	5.000s	57.978us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	682.724us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	682.724us	48	50	96.00
		aes_control_fi	30.000s	10.010ms	285	300	95.00
		aes_cipher_fi	31.000s	10.003ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	31.000s	10.003ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	682.724us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	682.724us	48	50	96.00
		aes_control_fi	30.000s	10.010ms	285	300	95.00
		aes_ctr_fi	5.000s	57.978us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	682.724us	48	50	96.00
		aes_control_fi	30.000s	10.010ms	285	300	95.00
		aes_cipher_fi	31.000s	10.003ms	324	350	92.57
		aes_ctr_fi	5.000s	57.978us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	192.103us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	682.724us	48	50	96.00
		aes_control_fi	30.000s	10.010ms	285	300	95.00
		aes_cipher_fi	31.000s	10.003ms	324	350	92.57
		aes_ctr_fi	5.000s	57.978us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	682.724us	48	50	96.00
		aes_control_fi	30.000s	10.010ms	285	300	95.00
		aes_cipher_fi	31.000s	10.003ms	324	350	92.57
		aes_ctr_fi	5.000s	57.978us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	682.724us	48	50	96.00
		aes_control_fi	30.000s	10.010ms	285	300	95.00
		aes_ctr_fi	5.000s	57.978us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	682.724us	48	50	96.00
		aes_control_fi	30.000s	10.010ms	285	300	95.00
		aes_cipher_fi	31.000s	10.003ms	324	350	92.57
V2S		TOTAL			939	985	95.33
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	20.000s	1.633ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1546	1602	96.50

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.40	97.75	94.93	98.84	93.63	98.07	93.33	98.85	98.59

Failure Buckets

Job timed out after * minutes has 27 failures:
- Test aes_control_fi has 10 failures.
  - 15.aes_control_fi.67542022396667301695900846202411494888194170584053588214052260260656489858981
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 16.aes_control_fi.106379167206858266029105816385128821742096061271532939837019084804531011069564
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 16 failures.
  - 28.aes_cipher_fi.28104706345508331780271153767991238825709916197414551995434061077772398662020
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 34.aes_cipher_fi.62129845150507014326166445066044950313545909013396371914869629631530093199537
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 14 more failures.
- Test aes_fi has 1 failures.
  - 35.aes_fi.47118120565680209291432852046487920922805600427891105135002133816462153391913
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/35.aes_fi/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 5.aes_cipher_fi.112373704297255014022174880449757022679159705021080233265570381468488327483495
    Line 144, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011815812 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011815812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 16.aes_cipher_fi.105813861637455751209976425854762898026082860400326481702777663399977399547163
    Line 136, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007985227 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007985227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.4487088403820956134176834379674851286487952655243128377660149604103061278219
Line 652, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 989899641 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 989899641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.77498829960825394312254922679747558591928144890324276587987616439799328316162
Line 1336, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1632900854 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1632900854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 26.aes_control_fi.47963057743413150948810817428682192189262803380638711849024047360698168747382
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003526815 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003526815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 106.aes_control_fi.109130183607189509185528362610864300032483820050481342417728584995837749650639
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/106.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10019696289 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019696289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 1.aes_stress_all_with_rand_reset.74865986645715644574644223454096151004104940950002178226792679002217806648223
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  16678642 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  16678642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.aes_stress_all_with_rand_reset.69433023486408387765696885916131500287443704806770336539128814147364316394065
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  48988143 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  48988143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 15.aes_core_fi.24171560822751998107582873590128649025594039126731078820427684254205724404375
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10049472766 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10049472766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 53.aes_core_fi.22335310474785683310726489234738819437537807969755197910219695867175492260007
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021830851 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021830851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.23825675326284659148911915177883851661785192813262380577337666249415301599596
    Line 149, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  30221864 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  30221864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 20.aes_core_fi.66048705396246203672847802829950053065700469154149664071374742438707706794033
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012440962 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012440962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

37.aes_fi.107065315081875450221562109812575461669924611241908928399736563537906355634891
Line 1315, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/37.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 6409470 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 6399369 PS)
  UVM_ERROR @   6409470 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   6409470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---