CSRNG Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: `2211fb0`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	348.537us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	187.739us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	302.320us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	40.000s	2.146ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	42.576us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	217.163us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	302.320us	20	20	100.00
		csrng_csr_aliasing	7.000s	42.576us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	1.068ms	163	200	81.50
V2	alerts	csrng_alert	1.050m	5.238ms	500	500	100.00
V2	err	csrng_err	10.000s	21.952us	444	500	88.80
V2	cmds	csrng_cmds	5.333m	24.585ms	50	50	100.00
V2	life cycle	csrng_cmds	5.333m	24.585ms	50	50	100.00
V2	stress_all	csrng_stress_all	20.317m	70.305ms	48	50	96.00
V2	intr_test	csrng_intr_test	6.000s	132.085us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	159.039us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	620.498us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	620.498us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	187.739us	5	5	100.00
		csrng_csr_rw	8.000s	302.320us	20	20	100.00
		csrng_csr_aliasing	7.000s	42.576us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	263.805us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	187.739us	5	5	100.00
		csrng_csr_rw	8.000s	302.320us	20	20	100.00
		csrng_csr_aliasing	7.000s	42.576us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	263.805us	20	20	100.00
V2		TOTAL			1345	1440	93.40
V2S	tl_intg_err	csrng_sec_cm	7.000s	64.937us	5	5	100.00
		csrng_tl_intg_err	16.000s	1.180ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	104.660us	50	50	100.00
		csrng_csr_rw	8.000s	302.320us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.050m	5.238ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	20.317m	70.305ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
		csrng_sec_cm	7.000s	64.937us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
		csrng_sec_cm	7.000s	64.937us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
		csrng_sec_cm	7.000s	64.937us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
		csrng_sec_cm	7.000s	64.937us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
		csrng_sec_cm	7.000s	64.937us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
		csrng_sec_cm	7.000s	64.937us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
		csrng_sec_cm	7.000s	64.937us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.050m	5.238ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	20.317m	70.305ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.050m	5.238ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	1.180ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
		csrng_sec_cm	7.000s	64.937us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
		csrng_sec_cm	7.000s	64.937us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	1.068ms	163	200	81.50
		csrng_err	10.000s	21.952us	444	500	88.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	3.567m	12.206ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1525	1630	93.56

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.65	98.58	96.56	99.91	97.48	92.15	88.00	96.31	89.94

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_control_fsm.sv,452): Assertion u_state_regs_A has failed has 51 failures:

Test csrng_intr has 19 failures.

1.csrng_intr.12733259776934186644445054451617898873111465551147503823157751586900140491543
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 351779517 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[1].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @ 351779517 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 351779517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.csrng_intr.106761831293983874724343916330516412199153051523271388417814924607933745226432
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/40.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 143730912 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @ 143730912 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 143730912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

Test csrng_err has 32 failures.

10.csrng_err.33272178822238090680874208708292650223889532867078745070501196094249082280037
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/10.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 22592428 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[0].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @  22592428 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  22592428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.csrng_err.33162120587966822271951593805349762389678125741567363527598111598382399916566
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/29.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 7254120 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[0].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @   7254120 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   7254120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 30 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,188): Assertion u_blk_enc_state_regs_A has failed has 11 failures:

Test csrng_intr has 4 failures.

39.csrng_intr.40643756973932192343578322714761032527188891032371910195239512328999466748940
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/39.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 46109063 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @  46109063 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @  46109063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

93.csrng_intr.46918366007751617675423424791232197957446732472619954450471168296301641939332
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/93.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 143175025 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @ 143175025 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @ 143175025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test csrng_err has 7 failures.

104.csrng_err.47082404476802579068310185322639655741238734694905530141109791350838893645830
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/104.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 2221111 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @   2221111 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @   2221111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

173.csrng_err.42452420705079466117214885282741399300182448532142848426394068337440675699837
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/173.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 1716871 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @   1716871 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @   1716871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,222): Assertion u_outblk_state_regs_A has failed has 11 failures:

Test csrng_err has 6 failures.

70.csrng_err.65676004607048186779434032530192318482824017471634818310284060505880592703930
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/70.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 20120121 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @  20120121 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @  20120121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

203.csrng_err.99852613018997324487962675855372665481280441331944134263021063381186512921069
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/203.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 1756854 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @   1756854 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @   1756854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test csrng_intr has 5 failures.

74.csrng_intr.14997201002449251634372783566213362701356879741640862006555774765116536507907
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/74.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 234204935 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @ 234204935 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @ 234204935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

83.csrng_intr.89636156078201321419525466194306419892645984923384703262285486732160205064885
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/83.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 761517596 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @ 761517596 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @ 761517596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 0.csrng_stress_all_with_rand_reset.36362339941921640722595032940862604463939344506355425856799657728572780144597
    Line 109, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2546388540 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2546388540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.66095388883220213419777935932723804477425235791857752033099389461148851457203
    Line 102, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9103545259 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9103545259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_gen.sv,222): Assertion u_state_regs_A has failed has 10 failures:

Test csrng_err has 8 failures.

9.csrng_err.75414017098954794221943834357062088574180715139415187976565763788391613047546
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/9.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 13763192 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @  13763192 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  13763192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.csrng_err.91828545860641049704749199922905882141502913925561634799417713157372547041845
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/12.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 26590139 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @  26590139 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  26590139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test csrng_intr has 2 failures.

130.csrng_intr.13310882990528989936626990524605723281693110027403917206236196058195339799153
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/130.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 403471827 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @ 403471827 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 403471827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

199.csrng_intr.72935699225938510987677819806048809069760660211391410421135311257708285404857
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/199.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 181009311 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @ 181009311 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 181009311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_main_sm.sv,35): Assertion u_state_regs_A has failed has 6 failures:

Test csrng_err has 3 failures.

4.csrng_err.27960241816091971708736842365214889212657169089244715940351276966599231066045
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/4.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 7265862 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @   7265862 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   7265862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

385.csrng_err.37155355025776621098756134986035140533537230323322942598654183518056485332418
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/385.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 1871155 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @   1871155 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   1871155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test csrng_intr has 3 failures.

89.csrng_intr.93485657575163699319701930412337674410567461585332311721407351188415356855433
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/89.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 220873647 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @ 220873647 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 220873647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

162.csrng_intr.90280929654629416426928675941052805619511916805317919912761909895031632436852
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/162.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 278575819 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @ 278575819 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 278575819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,260): Assertion u_state_regs_A has failed has 3 failures:

Test csrng_intr has 3 failures.

54.csrng_intr.86545985430917335429713952792336860958420889462650398738450971807542473679933
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/54.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,260): (time 77211564 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.u_state_regs_A has failed
  UVM_ERROR @  77211564 ps: (csrng_cmd_stage.sv:260) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  77211564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

91.csrng_intr.28593358394347969348589025104937186726349411311734693052514684952062163329282
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/91.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,260): (time 44011806 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.u_state_regs_A has failed
  UVM_ERROR @  44011806 ps: (csrng_cmd_stage.sv:260) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  44011806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

20.csrng_stress_all.46079277634501797814673424054218591854491785140269915208844235201837794674266
Line 141, in log /nightly/runs/scratch/master/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log

  UVM_ERROR @ 3473796162 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3473796162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.csrng_stress_all.27436894964759556108707907009231441689730541735639279238204823938909385972934
Line 141, in log /nightly/runs/scratch/master/csrng-sim-xcelium/29.csrng_stress_all/latest/run.log

  UVM_ERROR @ 7764073378 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 7764073378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

28.csrng_intr.55347618714761981275195041471787736012672214714412324249490027953618099953137
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/28.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 113637076 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 113637076 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 113637076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---