DMA Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	11.000s	1.235ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	13.000s	618.098us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	13.000s	1.603ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	36.000s	62.281us	5	5	100.00
V1	csr_rw	dma_csr_rw	36.000s	19.655us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	46.000s	293.887us	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	38.000s	462.216us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	34.000s	165.172us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	36.000s	19.655us	20	20	100.00
		dma_csr_aliasing	38.000s	462.216us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.950m	10.491ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	8.317m	399.023ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	5.950m	100.179ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	38.400m	234.392ms	4	5	80.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	8.317m	399.023ms	3	3	100.00
V2	dma_abort	dma_abort	14.000s	577.869us	5	5	100.00
V2	dma_stress_all	dma_stress_all	3.733m	59.813ms	3	3	100.00
V2	intr_test	dma_intr_test	36.000s	44.751us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	38.000s	222.633us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	38.000s	222.633us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	36.000s	62.281us	5	5	100.00
		dma_csr_rw	36.000s	19.655us	20	20	100.00
		dma_csr_aliasing	38.000s	462.216us	5	5	100.00
		dma_same_csr_outstanding	37.000s	363.227us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	36.000s	62.281us	5	5	100.00
		dma_csr_rw	36.000s	19.655us	20	20	100.00
		dma_csr_aliasing	38.000s	462.216us	5	5	100.00
		dma_same_csr_outstanding	37.000s	363.227us	20	20	100.00
V2		TOTAL			113	114	99.12
V2S	dma_illegal_addr_range	dma_mem_enabled	33.000s	258.458us	5	5	100.00
		dma_generic_stress	38.400m	234.392ms	4	5	80.00
		dma_handshake_stress	8.317m	399.023ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	39.000s	230.390us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.750m	32.258ms	5	5	100.00
		dma_longer_transfer	7.000s	682.281us	5	5	100.00
		TOTAL			303	304	99.67

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.12	96.97	95.19	96.28	96.02	77.31	82.76	97.77	41.23

Failure Buckets

• Job timed out after * minutes has 1 failures:
  • Test dma_generic_stress has 1 failures.

    • 3.dma_generic_stress.84323891838431923158780992464451751253963041828687807652063988283090483137627
      Log /nightly/runs/scratch/master/dma-sim-xcelium/3.dma_generic_stress/latest/run.log

        Job timed out after 60 minutes