EDN Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.600s 18.437us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 3.080s 17.074us 5 5 100.00
V1 csr_rw edn_csr_rw 2.950s 45.680us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.930s 1.668ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 3.380s 175.807us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 3.400s 30.658us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.950s 45.680us 20 20 100.00
edn_csr_aliasing 3.380s 175.807us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.064m 4.396ms 300 300 100.00
V2 csrng_commands edn_genbits 1.064m 4.396ms 300 300 100.00
V2 genbits edn_genbits 1.064m 4.396ms 300 300 100.00
V2 interrupts edn_intr 2.640s 24.068us 50 50 100.00
V2 alerts edn_alert 2.810s 26.143us 200 200 100.00
V2 errs edn_err 2.840s 25.286us 100 100 100.00
V2 disable edn_disable 2.510s 31.547us 50 50 100.00
edn_disable_auto_req_mode 2.800s 93.204us 50 50 100.00
V2 stress_all edn_stress_all 10.590s 448.265us 50 50 100.00
V2 intr_test edn_intr_test 2.930s 83.241us 50 50 100.00
V2 alert_test edn_alert_test 2.760s 109.529us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.830s 203.444us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.830s 203.444us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 3.080s 17.074us 5 5 100.00
edn_csr_rw 2.950s 45.680us 20 20 100.00
edn_csr_aliasing 3.380s 175.807us 5 5 100.00
edn_same_csr_outstanding 3.130s 19.658us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 3.080s 17.074us 5 5 100.00
edn_csr_rw 2.950s 45.680us 20 20 100.00
edn_csr_aliasing 3.380s 175.807us 5 5 100.00
edn_same_csr_outstanding 3.130s 19.658us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 11.200s 3.416ms 5 5 100.00
edn_tl_intg_err 4.520s 515.492us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.440s 21.733us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.810s 26.143us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 11.200s 3.416ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 11.200s 3.416ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 11.200s 3.416ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 11.200s 3.416ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.810s 26.143us 200 200 100.00
edn_sec_cm 11.200s 3.416ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.810s 26.143us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.520s 515.492us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.641m 19.979ms 34 50 68.00
V3 TOTAL 34 50 68.00
TOTAL 1114 1130 98.58

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.95 98.87 94.29 97.02 92.44 96.33 99.78 92.94

Failure Buckets