HMAC Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	12.040s	1.955ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.460s	80.924us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.320s	37.868us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.270s	19.604ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.720s	1.209ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.054m	114.244ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.320s	37.868us	20	20	100.00
		hmac_csr_aliasing	8.720s	1.209ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.616m	3.745ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.566m	18.272ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.120m	6.033ms	30	30	100.00
		hmac_test_sha384_vectors	9.329m	59.234ms	75	75	100.00
		hmac_test_sha512_vectors	9.444m	16.712ms	75	75	100.00
		hmac_test_hmac256_vectors	16.720s	669.713us	50	50	100.00
		hmac_test_hmac384_vectors	16.700s	383.289us	60	60	100.00
		hmac_test_hmac512_vectors	19.800s	2.561ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	44.500s	13.052ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	21.920m	15.650ms	10	10	100.00
V2	error	hmac_error	2.315m	9.743ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.744m	35.030ms	10	10	100.00
V2	save_and_restore	hmac_smoke	12.040s	1.955ms	10	10	100.00
		hmac_long_msg	1.616m	3.745ms	10	10	100.00
		hmac_back_pressure	1.566m	18.272ms	25	25	100.00
		hmac_datapath_stress	21.920m	15.650ms	10	10	100.00
		hmac_burst_wr	44.500s	13.052ms	50	50	100.00
		hmac_stress_all	41.007m	111.997ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	12.040s	1.955ms	10	10	100.00
		hmac_long_msg	1.616m	3.745ms	10	10	100.00
		hmac_back_pressure	1.566m	18.272ms	25	25	100.00
		hmac_datapath_stress	21.920m	15.650ms	10	10	100.00
		hmac_wipe_secret	1.744m	35.030ms	10	10	100.00
		hmac_test_sha256_vectors	4.120m	6.033ms	30	30	100.00
		hmac_test_sha384_vectors	9.329m	59.234ms	75	75	100.00
		hmac_test_sha512_vectors	9.444m	16.712ms	75	75	100.00
		hmac_test_hmac256_vectors	16.720s	669.713us	50	50	100.00
		hmac_test_hmac384_vectors	16.700s	383.289us	60	60	100.00
		hmac_test_hmac512_vectors	19.800s	2.561ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	12.040s	1.955ms	10	10	100.00
		hmac_long_msg	1.616m	3.745ms	10	10	100.00
		hmac_back_pressure	1.566m	18.272ms	25	25	100.00
		hmac_datapath_stress	21.920m	15.650ms	10	10	100.00
		hmac_burst_wr	44.500s	13.052ms	50	50	100.00
		hmac_error	2.315m	9.743ms	10	10	100.00
		hmac_wipe_secret	1.744m	35.030ms	10	10	100.00
		hmac_test_sha256_vectors	4.120m	6.033ms	30	30	100.00
		hmac_test_sha384_vectors	9.329m	59.234ms	75	75	100.00
		hmac_test_sha512_vectors	9.444m	16.712ms	75	75	100.00
		hmac_test_hmac256_vectors	16.720s	669.713us	50	50	100.00
		hmac_test_hmac384_vectors	16.700s	383.289us	60	60	100.00
		hmac_test_hmac512_vectors	19.800s	2.561ms	75	75	100.00
		hmac_stress_all	41.007m	111.997ms	50	50	100.00
V2	stress_all	hmac_stress_all	41.007m	111.997ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.170s	24.323us	50	50	100.00
V2	intr_test	hmac_intr_test	2.180s	18.132us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.370s	73.710us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.370s	73.710us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.460s	80.924us	5	5	100.00
		hmac_csr_rw	2.320s	37.868us	20	20	100.00
		hmac_csr_aliasing	8.720s	1.209ms	5	5	100.00
		hmac_same_csr_outstanding	3.260s	46.717us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.460s	80.924us	5	5	100.00
		hmac_csr_rw	2.320s	37.868us	20	20	100.00
		hmac_csr_aliasing	8.720s	1.209ms	5	5	100.00
		hmac_same_csr_outstanding	3.260s	46.717us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.710s	97.183us	5	5	100.00
		hmac_tl_intg_err	6.160s	3.294ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.160s	3.294ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	12.040s	1.955ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.460s	264.640us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.416m	77.722ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	1.890s	37.540us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.09	100.00	97.31	100.00	100.00	100.00	100.00	47.30