2211fb0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.672m | 12.997ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 32.510s | 1.334ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 2.170s | 19.693us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 2.150s | 21.711us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.590s | 3.058ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 3.170s | 95.525us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.770s | 102.600us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 2.150s | 21.711us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 3.170s | 95.525us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 22.560s | 501.582us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 32.439m | 139.974ms | 19 | 50 | 38.00 |
| V2 | host_maxperf | i2c_host_perf | 32.759m | 53.260ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 2.460s | 20.911us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.772m | 21.115ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.315m | 3.459ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.810s | 154.128us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 25.020s | 2.795ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 11.180s | 1.596ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 2.825m | 6.147ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 44.230s | 4.250ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.220s | 171.882us | 18 | 50 | 36.00 |
| V2 | target_glitch | i2c_target_glitch | 9.150s | 2.207ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 21.765m | 53.500ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 9.660s | 2.024ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.178m | 3.621ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 11.620s | 1.419ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.550s | 1.012ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.430s | 239.532us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 26.594m | 67.868ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.178m | 3.621ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.205m | 32.276ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 11.830s | 5.783ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.172m | 3.985ms | 50 | 50 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 10.320s | 6.368ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 38.370s | 10.014ms | 24 | 50 | 48.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.970s | 3.341ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 3.370s | 2.280ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 32.759m | 53.260ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 2.428m | 6.244ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 44.230s | 4.250ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 29.220s | 1.997ms | 47 | 50 | 94.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.630s | 2.434ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.160s | 583.555us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 3.480s | 367.207us | 32 | 50 | 64.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 37.780s | 2.224ms | 50 | 50 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.860s | 2.120ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 2.410s | 48.498us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 2.300s | 18.396us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.340s | 285.816us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.340s | 285.816us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 2.170s | 19.693us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.150s | 21.711us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.170s | 95.525us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.770s | 51.933us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 2.170s | 19.693us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.150s | 21.711us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.170s | 95.525us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.770s | 51.933us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1680 | 1792 | 93.75 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.860s | 137.496us | 20 | 20 | 100.00 |
| i2c_sec_cm | 2.570s | 75.752us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.860s | 137.496us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 49.440s | 1.207ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.970s | 977.204us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 27.440s | 9.927ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1860 | 2042 | 91.09 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.99 | 97.47 | 89.59 | 74.17 | 72.02 | 94.18 | 98.52 | 89.96 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 45 failures:
0.i2c_host_stress_all.87498738971964266939918639830178356136886486431653191589802120620599535938641
Line 152, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 76618866838 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @16685054
3.i2c_host_stress_all.2851307045179692709892487862544763981844916904257635529213194821463671426345
Line 268, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 16928250360 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10438618
... and 26 more failures.
7.i2c_host_mode_toggle.18307320374517709283052286085320140959686181916015946374152511990233086104868
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 152791226 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @12907
12.i2c_host_mode_toggle.24101557091833808790059421150445111237785392272676764457105828383289277229395
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 133569922 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @120201
... and 15 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 26 failures:
0.i2c_target_unexp_stop.62397895711562811961114994580617427412682705344754732394248019060824684649908
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 507700721 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 142 [0x8e])
UVM_INFO @ 507700721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.32993517869511850491721666930288952818988353114292898852834327831260938459938
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 134395491 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 245 [0xf5])
UVM_INFO @ 134395491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
7.i2c_target_stress_all_with_rand_reset.92990441907451849007849895689095760684003370511506457925899152763844853592051
Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12188453 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (47 [0x2f] vs 0 [0x0])
UVM_INFO @ 12188453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
3.i2c_target_hrst.43547126477451210913606688472734822971622852143149152197420666990404524502323
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10718099956 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10718099956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_hrst.102017622479674421597800527374307818785905569995557263272570014731917492849229
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10016283961 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10016283961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 18 failures:
1.i2c_target_unexp_stop.38797273870733876490415749198590237745029091151402977666082693405335461312491
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1430741412 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1430741412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.32214482253489035683361924414915405236617307986758587895254126151559536837658
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 68064503 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 68064503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 18 failures:
3.i2c_target_nack_txstretch.31638966993182301385294236351197623954558745631493141383850866274851378279021
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 167414266 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 167414266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_nack_txstretch.82931360631223569532499449271399016735157635316681021280160140029127185349865
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 426112283 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 426112283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.i2c_host_stress_all_with_rand_reset.95364933802557585471770308883220275689893071507275346880000612441255161887561
Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3709810190 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3709810190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.1089372842657438592345605755273178807152532753521364909669471908149935544046
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1300959239 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1300959239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.17254151641243021584101193598256377403884646828877821133842399229359986751712
Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1029366982 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1029366982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.42712218812204410341008408678317587308015315515231657662887467244671517115448
Line 90, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 996360033 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 996360033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:
0.i2c_host_mode_toggle.7494134710303730186072880629916784048093309167426680628377965271160259138104
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 142189973 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
3.i2c_host_mode_toggle.53819876602819964082013795319341891438660726878422973660950402303988992598128
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 344767884 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 11 more failures.
13.i2c_host_perf_precise.110567622443818052419295320868482068045414252978791226892584466113433354153064
Line 77, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_host_perf_precise/latest/run.log
UVM_ERROR @ 5612679372 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:
7.i2c_target_unexp_stop.85230813442323777904775288909256246059646837581335866340448745009904386135914
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 536313082 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 536313082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.59073826900395188968958688919254373791593722932762943349991715075989815137244
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 977203774 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 977203774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
7.i2c_target_tx_stretch_ctrl.107329715343071526351514767837202315085451705404046483012339321301996812991454
Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
46.i2c_target_tx_stretch_ctrl.6500539546180269288153056104181303908788805328422308921655229687164941867263
Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
Job timed out after * minutes has 2 failures:
7.i2c_host_stress_all.95161484427235064861385359672218844109377154662692726262306649362750043446896
Log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
43.i2c_host_stress_all.25144169913331522438349268047656223917365048817433164601639906470160492996113
Log /nightly/runs/scratch/master/i2c-sim-vcs/43.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
27.i2c_host_mode_toggle.114194804351917935138316382555676573544712055070537133665751832908001197482636
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/27.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 98020868 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xd3445e94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 98020868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.i2c_host_mode_toggle.2372918120083120406444525366035242229360612559049466063635893280304888324707
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/44.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 48119784 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xe9287294, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 48119784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
1.i2c_target_stress_all_with_rand_reset.86350081388233121385473038798518192747814275815180448598421348574292619678134
Line 122, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1235431467 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1235431467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
3.i2c_target_stress_all_with_rand_reset.87684689408285342484609308700351114087670763149175262620597858113654108775442
Line 110, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 100767254 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 100767254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:
27.i2c_host_stress_all.15296967291823896099150412021630474878305440030891843213254531328065740723389
Line 252, in log /nightly/runs/scratch/master/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 86950146369 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2203550
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
27.i2c_target_intr_stress_wr.67180031972933841202945993344946134326795071004375200775721469228539515335963
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/27.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 32276049878 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 32276049878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---