KEYMGR Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: `2211fb0`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	29.080s	6.183ms	50	50	100.00
V1	random	keymgr_random	57.770s	9.403ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.510s	16.998us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.840s	27.261us	16	20	80.00
V1	csr_bit_bash	keymgr_csr_bit_bash	12.680s	2.772ms	3	5	60.00
V1	csr_aliasing	keymgr_csr_aliasing	7.080s	484.324us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.960s	134.169us	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.840s	27.261us	16	20	80.00
		keymgr_csr_aliasing	7.080s	484.324us	4	5	80.00
V1		TOTAL			144	155	92.90
V2	cfgen_during_op	keymgr_cfg_regwen	1.648m	5.546ms	50	50	100.00
V2	sideload	keymgr_sideload	27.730s	7.298ms	50	50	100.00
		keymgr_sideload_kmac	38.610s	1.977ms	49	50	98.00
		keymgr_sideload_aes	33.730s	3.762ms	50	50	100.00
		keymgr_sideload_otbn	39.000s	1.809ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	40.370s	7.838ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	19.710s	529.514us	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	5.690s	421.789us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.047m	9.793ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	22.190s	2.968ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	32.240s	4.919ms	50	50	100.00
V2	stress_all	keymgr_stress_all	7.651m	29.042ms	49	50	98.00
V2	intr_test	keymgr_intr_test	2.450s	36.415us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.330s	13.041us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.270s	547.007us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.270s	547.007us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.510s	16.998us	5	5	100.00
		keymgr_csr_rw	2.840s	27.261us	16	20	80.00
		keymgr_csr_aliasing	7.080s	484.324us	4	5	80.00
		keymgr_same_csr_outstanding	5.230s	381.583us	19	20	95.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.510s	16.998us	5	5	100.00
		keymgr_csr_rw	2.840s	27.261us	16	20	80.00
		keymgr_csr_aliasing	7.080s	484.324us	4	5	80.00
		keymgr_same_csr_outstanding	5.230s	381.583us	19	20	95.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
		keymgr_tl_intg_err	5.810s	419.035us	15	20	75.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.630s	649.518us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.630s	649.518us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.630s	649.518us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.630s	649.518us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	10.880s	472.643us	13	20	65.00
V2S	prim_count_check	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.810s	419.035us	15	20	75.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.630s	649.518us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.648m	5.546ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	57.770s	9.403ms	50	50	100.00
		keymgr_csr_rw	2.840s	27.261us	16	20	80.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	57.770s	9.403ms	50	50	100.00
		keymgr_csr_rw	2.840s	27.261us	16	20	80.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	57.770s	9.403ms	50	50	100.00
		keymgr_csr_rw	2.840s	27.261us	16	20	80.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	19.710s	529.514us	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	22.190s	2.968ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	22.190s	2.968ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	57.770s	9.403ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	32.610s	4.732ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	41.190s	5.818ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	19.710s	529.514us	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	41.190s	5.818ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	41.190s	5.818ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	41.190s	5.818ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.550s	949.816us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	41.190s	5.818ms	50	50	100.00
V2S		TOTAL			153	165	92.73
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.930s	1.600ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1063	1110	95.77

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.81	99.13	98.22	98.37	100.00	99.10	98.63	91.21

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 24 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 7 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.45344964862355396922922076766002058609810074851639669532689409953647381671196
Line 78, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @  60835620 ps: (keymgr_csr_assert_fpv.sv:484) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @  60835620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_shadow_reg_errors_with_csr_rw.88045350689874733815113100510226469258706144507534744231994730606453092313615
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @   6989043 ps: (keymgr_csr_assert_fpv.sv:400) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @   6989043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test keymgr_tl_intg_err has 5 failures.

0.keymgr_tl_intg_err.79053778945752361283526707967742922967027693758241226655966867881132749849510
Line 117, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @  89319851 ps: (keymgr_csr_assert_fpv.sv:484) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @  89319851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_tl_intg_err.12827103002736783163606762442823554908086734101358036592456249744658349636748
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @  10082038 ps: (keymgr_csr_assert_fpv.sv:448) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @  10082038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_bit_bash has 2 failures.

0.keymgr_csr_bit_bash.80384992485507826035299148658886943940310306242233689139967279136358787253555
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @ 225345097 ps: (keymgr_csr_assert_fpv.sv:484) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @ 225345097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_csr_bit_bash.93687919335321316633468688520389582611395781849979490904017624351608372721469
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @ 346872928 ps: (keymgr_csr_assert_fpv.sv:412) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @ 346872928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_rw has 4 failures.

2.keymgr_csr_rw.64440036682805382268984557124424133849282899996506400614484099236385442265824
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  15949401 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  15949401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_csr_rw.23359381241269180426384588416741839515922032097714119307564524801172304361864
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @  85435999 ps: (keymgr_csr_assert_fpv.sv:478) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @  85435999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test keymgr_csr_mem_rw_with_rand_reset has 4 failures.

2.keymgr_csr_mem_rw_with_rand_reset.24444545760354475344237580346747058391263943107004159520958774062422275484702
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @  17634969 ps: (keymgr_csr_assert_fpv.sv:490) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @  17634969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_csr_mem_rw_with_rand_reset.84640383847176518210132321520539222155435845439686843110699441018208628955545
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @  90252923 ps: (keymgr_csr_assert_fpv.sv:418) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @  90252923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 1.keymgr_stress_all_with_rand_reset.9969215320871389138894122440662799100869127048483165084702059985563407006414
    Line 894, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1097559339 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1097559339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.keymgr_stress_all_with_rand_reset.30886922124436506840800932238255016670566706008957808958590072040173906189459
    Line 439, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 284453833 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 284453833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_stress_all has 1 failures.
  - 26.keymgr_stress_all.66743557201513709935967313853474446443245150134744649134655809913054096482910
    Line 300, in log /nightly/runs/scratch/master/keymgr-sim-vcs/26.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 634101184 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 634101184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload_kmac has 1 failures.
  - 47.keymgr_sideload_kmac.33062317954744869987322019589866638959707171200546447040176086110648255334824
    Line 83, in log /nightly/runs/scratch/master/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest/run.log
```
  UVM_ERROR @   8372428 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   8372428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Sealing Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

23.keymgr_lc_disable.65814470805715427657048335051191817849111276254014378267073881582493591285210
Line 449, in log /nightly/runs/scratch/master/keymgr-sim-vcs/23.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 183162618 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10505877618538222937668789059514101427829510002181371345728776613757036993652105579803257371491999746806267704761049834479455665549672216717692545809984271 [0xc897a8fcd2727a88101f13f7342c9c332cf9f879b74db3529cca1e5f62053e37546f23e9bf5b6f2a6746035fc49e7bbb342db6acc56da39c0a1a600db0532b0f] vs 10505877618538222937668789059514101427829510002181371345728776613757036993652105579803257371491999746806267704761049834479455665549672216717692545809984271 [0xc897a8fcd2727a88101f13f7342c9c332cf9f879b74db3529cca1e5f62053e37546f23e9bf5b6f2a6746035fc49e7bbb342db6acc56da39c0a1a600db0532b0f]) KMAC key at state StDisabled for Sealing Kmac
  UVM_INFO @ 183162618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 41.keymgr_lc_disable.106851878119555166762459788866823496027728873304510083885404346445632387402427
    Line 244, in log /nightly/runs/scratch/master/keymgr-sim-vcs/41.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @ 219952329 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_3
  UVM_INFO @ 219952329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```