KEYMGR_DPE Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	4.136m	80.769ms	47	50	94.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	2.660s	27.627us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	2.880s	113.736us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	18.990s	854.999us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	6.510s	2.804ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	3.350s	146.285us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	2.880s	113.736us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.510s	2.804ms	5	5	100.00
V1		TOTAL			101	105	96.19
V2	intr_test	keymgr_dpe_intr_test	2.310s	43.492us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	2.470s	15.423us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	6.950s	2.395ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	6.950s	2.395ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	2.660s	27.627us	5	5	100.00
		keymgr_dpe_csr_rw	2.880s	113.736us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.510s	2.804ms	5	5	100.00
		keymgr_dpe_same_csr_outstanding	4.360s	95.653us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	2.660s	27.627us	5	5	100.00
		keymgr_dpe_csr_rw	2.880s	113.736us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.510s	2.804ms	5	5	100.00
		keymgr_dpe_same_csr_outstanding	4.360s	95.653us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	12.370s	2.278ms	5	5	100.00
		keymgr_dpe_tl_intg_err	8.100s	876.809us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	4.460s	120.167us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	4.460s	120.167us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	4.460s	120.167us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	4.460s	120.167us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	9.160s	2.659ms	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	12.370s	2.278ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	12.370s	2.278ms	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			306	310	98.71

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.07	97.63	90.70	63.14	76.92	94.89	98.57	17.64

Failure Buckets

• UVM_ERROR (keymgr_dpe_scoreboard.sv:565) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 3 failures:
  • Test keymgr_dpe_smoke has 3 failures.

    • 7.keymgr_dpe_smoke.45377996473579858000818600566780452266257330988749421967688121419169485904489
      Line 2327, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/7.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 430032122 ps: (keymgr_dpe_scoreboard.sv:565) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h813dd1b7b51fdf3569b1e0253ceacd2111f6fd71f8ddc659b986037071e165877d448b984ffe211df0c11650617538be15b19bab33151aba5e671a5b33ccba25 vs. act 'h0
        UVM_INFO @ 430032122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 19.keymgr_dpe_smoke.58687652057801299347969190335681686537547003027873848745021929674942478958351
      Line 2953, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/19.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 6857940073 ps: (keymgr_dpe_scoreboard.sv:565) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'he16d113215de18b72328a5853a2ab197f66bc84c9f9929b960f8f3494025097e30f671acdd02a6a01682ee9fc7f50b3f1af836483d4964a6e4f5e8fe6c69ad41 vs. act 'h0
        UVM_INFO @ 6857940073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: * has 1 failures:
  • Test keymgr_dpe_csr_mem_rw_with_rand_reset has 1 failures.

    • 4.keymgr_dpe_csr_mem_rw_with_rand_reset.102378846969165195039648427679520094632593913971872117596776913459948085231553
      Line 92, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 115123763 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
        UVM_INFO @ 115123763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---