KMAC/MASKED Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.584m	3.910ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.340s	69.942us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.590s	47.111us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.000s	8.764ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.970s	537.632us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.810s	66.755us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.590s	47.111us	20	20	100.00
		kmac_csr_aliasing	7.970s	537.632us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.020s	29.256us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.800s	414.934us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.979m	86.714ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.645m	39.198ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.016m	335.309ms	5	5	100.00
		kmac_test_vectors_sha3_256	38.695m	86.205ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.878m	90.889ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.152m	41.875ms	5	5	100.00
		kmac_test_vectors_shake_128	43.386m	480.610ms	5	5	100.00
		kmac_test_vectors_shake_256	40.535m	351.460ms	5	5	100.00
		kmac_test_vectors_kmac	5.190s	598.388us	5	5	100.00
		kmac_test_vectors_kmac_xof	7.170s	439.914us	5	5	100.00
V2	sideload	kmac_sideload	9.269m	20.677ms	50	50	100.00
V2	app	kmac_app	7.063m	231.692ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.308m	7.901ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.072m	35.271ms	50	50	100.00
V2	error	kmac_error	7.650m	15.520ms	50	50	100.00
V2	key_error	kmac_key_error	18.860s	1.961ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	12.410s	852.946us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.770s	1.195ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.460s	513.840us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.104m	19.322ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.110m	4.112ms	50	50	100.00
V2	stress_all	kmac_stress_all	49.939m	237.761ms	49	50	98.00
V2	intr_test	kmac_intr_test	2.220s	16.737us	50	50	100.00
V2	alert_test	kmac_alert_test	2.350s	16.341us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.670s	133.450us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.670s	133.450us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.340s	69.942us	5	5	100.00
		kmac_csr_rw	2.590s	47.111us	20	20	100.00
		kmac_csr_aliasing	7.970s	537.632us	5	5	100.00
		kmac_same_csr_outstanding	4.210s	99.343us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.340s	69.942us	5	5	100.00
		kmac_csr_rw	2.590s	47.111us	20	20	100.00
		kmac_csr_aliasing	7.970s	537.632us	5	5	100.00
		kmac_same_csr_outstanding	4.210s	99.343us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.200s	248.567us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.200s	248.567us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.200s	248.567us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.200s	248.567us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.950s	371.213us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	2.395m	36.109ms	5	5	100.00
		kmac_tl_intg_err	6.400s	197.939us	13	20	65.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.400s	197.939us	13	20	65.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.110m	4.112ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.584m	3.910ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.269m	20.677ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.200s	248.567us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.395m	36.109ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.395m	36.109ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.395m	36.109ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.584m	3.910ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.110m	4.112ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.395m	36.109ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.648m	23.654ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.584m	3.910ms	50	50	100.00
V2S		TOTAL			64	75	85.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.719m	25.941ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			926	940	98.51

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.52	99.14	94.47	99.89	80.99	97.09	99.38	97.72

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 11 failures:

  • Test kmac_tl_intg_err has 7 failures.

    • 0.kmac_tl_intg_err.2524872441221133599190174016601867585212439121644124578565528092084411152034
      Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  10369677 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  10369677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.kmac_tl_intg_err.41525745656757050134143944973097935919473159105792457678126902824809063219550
      Line 101, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
        UVM_ERROR @  67161749 ps: (kmac_csr_assert_fpv.sv:560) [ASSERT FAILED] prefix_10_rd_A
        UVM_INFO @  67161749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

  • Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

    • 1.kmac_shadow_reg_errors_with_csr_rw.99337017985532795680568486362486658536441646424850564005747132608398943135091
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  26925056 ps: (kmac_csr_assert_fpv.sv:518) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  26925056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.kmac_shadow_reg_errors_with_csr_rw.22385698956275834094478802921989096210426272183698032381570027350192530955901
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  13410401 ps: (kmac_csr_assert_fpv.sv:518) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  13410401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 3.kmac_stress_all_with_rand_reset.63710879220376150727269214862796316153161573710840085757399195517877271400840
      Line 163, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3271186008 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3271186008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.kmac_stress_all_with_rand_reset.18926022699703478798861878621822641869043944049268331780926750283593471800170
      Line 91, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 745132376 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 745132376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_stress_all has 1 failures.

    • 35.kmac_stress_all.45378215363652476634203661568645699299349020053964513311666622270982590433117
      Line 238, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/35.kmac_stress_all/latest/run.log

        UVM_ERROR @ 37766547718 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 37766547718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---