2211fb0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.164m | 14.698ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 2.470s | 28.291us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 2.370s | 235.314us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 8.730s | 1.947ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 7.540s | 333.471us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 3.500s | 915.022us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 2.370s | 235.314us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 7.540s | 333.471us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 2.370s | 39.221us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 2.900s | 256.462us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 47.898m | 598.756ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 16.865m | 151.047ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 22.117m | 35.895ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 28.088m | 82.923ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 20.805m | 89.297ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 15.877m | 260.680ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 34.918m | 218.873ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 19.824m | 17.534ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 3.780s | 67.503us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 4.080s | 76.330us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 8.226m | 42.138ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 5.434m | 77.467ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 6.080m | 122.426ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 5.820m | 82.545ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 6.804m | 57.608ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 16.320s | 14.398ms | 50 | 50 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 2.208m | 10.058ms | 31 | 50 | 62.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 47.090s | 4.600ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 50.260s | 2.357ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.064m | 10.608ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 34.360s | 2.875ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 37.540m | 510.214ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 2.280s | 21.880us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 2.380s | 35.232us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.450s | 690.802us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.450s | 690.802us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 2.470s | 28.291us | 5 | 5 | 100.00 |
| kmac_csr_rw | 2.370s | 235.314us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 7.540s | 333.471us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.510s | 176.482us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 2.470s | 28.291us | 5 | 5 | 100.00 |
| kmac_csr_rw | 2.370s | 235.314us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 7.540s | 333.471us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.510s | 176.482us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 721 | 740 | 97.43 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.800s | 145.764us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.800s | 145.764us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.800s | 145.764us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.800s | 145.764us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 4.720s | 190.647us | 13 | 20 | 65.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.056m | 5.211ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 4.860s | 238.268us | 13 | 20 | 65.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 4.860s | 238.268us | 13 | 20 | 65.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 34.360s | 2.875ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.164m | 14.698ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.226m | 42.138ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.800s | 145.764us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.056m | 5.211ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.056m | 5.211ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.056m | 5.211ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.164m | 14.698ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 34.360s | 2.875ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.056m | 5.211ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.423m | 17.199ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.164m | 14.698ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 61 | 75 | 81.33 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 3.469m | 10.529ms | 4 | 10 | 40.00 |
| V3 | TOTAL | 4 | 10 | 40.00 | |||
| TOTAL | 901 | 940 | 95.85 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.65 | 97.23 | 94.42 | 100.00 | 72.73 | 95.98 | 99.35 | 95.84 |
Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 14 failures:
0.kmac_shadow_reg_errors_with_csr_rw.48484640413030784948345588512491959693249008604086354136659218653719900562555
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
UVM_ERROR @ 137354401 ps: (kmac_csr_assert_fpv.sv:518) [ASSERT FAILED] prefix_3_rd_A
UVM_INFO @ 137354401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_shadow_reg_errors_with_csr_rw.112234711169353119888415616691048043536071796046030557290732944274415413104886
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
UVM_ERROR @ 15217535 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_7_rd_A
UVM_INFO @ 15217535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
1.kmac_tl_intg_err.70112107780357437252606531632543021942548164222947446496347246530485779437632
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
UVM_ERROR @ 10384385 ps: (kmac_csr_assert_fpv.sv:536) [ASSERT FAILED] prefix_6_rd_A
UVM_INFO @ 10384385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.kmac_tl_intg_err.34437519554126133623707355913096921172172901665926857157352783822436933960029
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
UVM_ERROR @ 40996968 ps: (kmac_csr_assert_fpv.sv:518) [ASSERT FAILED] prefix_3_rd_A
UVM_INFO @ 40996968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 7 failures:
0.kmac_sideload_invalid.66132986431787001678176529405620868076803111986023606149174202070571897705461
Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10028189899 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8bd2a000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10028189899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_sideload_invalid.62416836532506440565074633577697009636418731723807824293607984582675234874002
Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10009492933 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa4248000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10009492933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
1.kmac_stress_all_with_rand_reset.45878897926271343512157289858964769680246347510714051791055015177243202499120
Line 244, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2271074846 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
UVM_INFO @ 2271074846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_stress_all_with_rand_reset.29431381054822962607767018392023538551651571576528009189257648511149356799606
Line 118, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1079619948 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
UVM_INFO @ 1079619948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 3 failures:
4.kmac_sideload_invalid.15103429580515402723106204589191694502881850618802743847372209243289050313623
Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 11011991848 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbc38c000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 11011991848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.kmac_sideload_invalid.1910505206699734910279620255083268887911171725660464801783619799344523624785
Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10058158497 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x98229000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10058158497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 2 failures:
15.kmac_sideload_invalid.87360192242421392661164883302905597989465270695191319446910993367632653162700
Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/15.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10233722121 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb5ab8000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10233722121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.kmac_sideload_invalid.93509089050198374093916819385733870290968257741438733824835546620994161295163
Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10207498347 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa5c61000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10207498347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:
19.kmac_sideload_invalid.41590550679288215117819541735400501763597873482944726094603828885641581657380
Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10168517620 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbff7000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10168517620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.kmac_sideload_invalid.4594734688436567873573647209345752194906146396388257978063719651830834991693
Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/30.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10264298195 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf4704000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10264298195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
6.kmac_sideload_invalid.98984156129216109243224448097964297951514443365052740377319917594823167084946
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10390373085 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8b05f000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10390373085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
8.kmac_sideload_invalid.70460394152779592644340581729435843329387154461598615065418285500982380414842
Line 96, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10467621950 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4eab5000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10467621950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
17.kmac_sideload_invalid.45988867899273069720383703331715362277036845826105812009875800823451644206333
Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10496761192 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x33fc1000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10496761192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
46.kmac_sideload_invalid.79379645429844965644114084850823039045606228173916228502356544156892184355654
Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/46.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10088537121 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x56217000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10088537121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
48.kmac_sideload_invalid.23499328558717297697620591386463215646946926918025901026298064390442325062672
Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10091788738 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x202000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10091788738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---