OTBN Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: `2211fb0`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	149.472us	1	1	100.00
V1	single_binary	otbn_single	33.000s	451.813us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	9.000s	19.521us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	10.352us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	39.530us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	16.539us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	61.766us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	10.352us	20	20	100.00
		otbn_csr_aliasing	8.000s	16.539us	5	5	100.00
V1	mem_walk	otbn_mem_walk	38.000s	7.415ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	21.000s	382.332us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	1.633m	672.193us	10	10	100.00
V2	multi_error	otbn_multi_err	58.000s	335.483us	1	1	100.00
V2	back_to_back	otbn_multi	8.450m	3.834ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.333m	282.324us	10	10	100.00
V2	lc_escalation	otbn_escalate	34.000s	111.554us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	19.908us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	21.000s	66.167us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	29.933us	50	50	100.00
V2	intr_test	otbn_intr_test	23.000s	82.762us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	40.000s	119.278us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	40.000s	119.278us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	9.000s	19.521us	5	5	100.00
		otbn_csr_rw	7.000s	10.352us	20	20	100.00
		otbn_csr_aliasing	8.000s	16.539us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	19.451us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	9.000s	19.521us	5	5	100.00
		otbn_csr_rw	7.000s	10.352us	20	20	100.00
		otbn_csr_aliasing	8.000s	16.539us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	19.451us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	16.000s	32.399us	10	10	100.00
		otbn_dmem_err	19.000s	107.387us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	37.000s	92.630us	5	5	100.00
		otbn_controller_ispr_rdata_err	18.000s	62.661us	5	5	100.00
		otbn_mac_bignum_acc_err	18.000s	79.042us	5	5	100.00
		otbn_urnd_err	11.000s	51.993us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	21.302us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	42.517us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	26.430us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	3.117m	752.859us	2	5	40.00
		otbn_tl_intg_err	57.000s	287.628us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.283m	284.604us	17	20	85.00
V2S	prim_fsm_check	otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	149.472us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	19.000s	107.387us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	32.399us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	57.000s	287.628us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	34.000s	111.554us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	32.399us	10	10	100.00
		otbn_dmem_err	19.000s	107.387us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	19.908us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	21.302us	5	5	100.00
		otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	33.000s	451.813us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	32.399us	10	10	100.00
		otbn_dmem_err	19.000s	107.387us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	19.908us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	21.302us	5	5	100.00
		otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	34.000s	111.554us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	32.399us	10	10	100.00
		otbn_dmem_err	19.000s	107.387us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	19.908us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	21.302us	5	5	100.00
		otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	33.000s	451.813us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	66.025us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	23.704us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	38.000s	103.154us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	38.000s	103.154us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	35.822us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	19.000s	180.126us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	32.000s	1.016ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	32.000s	1.016ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	28.394us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	33.000s	451.813us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	33.000s	451.813us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	33.000s	451.813us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	8.450m	3.834ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	33.000s	451.813us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	33.000s	451.813us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	20.335us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	33.000s	451.813us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.117m	752.859us	2	5	40.00
V2S		TOTAL			153	163	93.87
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.467m	3.131ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			565	585	96.58

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.10	99.65	96.08	99.73	93.43	93.32	100.00	98.19	99.57

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_sec_wipe_err has 3 failures.

0.otbn_sec_wipe_err.114246795288378653012459927898777692201960138530823962345640225310709118439467
Line 117, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 47745231 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  47745231 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  47745231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_wipe_err.72661126725737711656194973765584697283705375735594909645477182704582292601991
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 28393507 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  28393507 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  28393507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otbn_stack_addr_integ_chk has 1 failures.

4.otbn_stack_addr_integ_chk.28251378867135433664325555415650544812096357697295148805168919545180852860548
Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21518588 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  21518588 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  21518588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 4 failures:

Test otbn_passthru_mem_tl_intg_err has 2 failures.

2.otbn_passthru_mem_tl_intg_err.716641640144709732032995993224683307903951777740178739011009711607285137578
Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @  11680623 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  11680623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.otbn_passthru_mem_tl_intg_err.82452555960687064939122074646517102553548139517297027088254705887478745105404
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/15.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @   5249483 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @   5249483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_stress_all_with_rand_reset has 1 failures.

3.otbn_stress_all_with_rand_reset.113721897914424957472493854175515816044406395490938048467347539008268564755959
Line 359, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 1407183758 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @ 1407183758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_single has 1 failures.

45.otbn_single.69216466813205016387186794886537024013211934002672719925822572624125236502717
Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/45.otbn_single/latest/run.log

  UVM_FATAL @ 102325690 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @ 102325690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.82196628537699018935179955593702543854639730995092670653941184485731735754695
Line 83, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 5018564 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 5018564 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @   5018564 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @   5018564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_cm.73677274091063471562051594119530278592857236428953191375895256484936051929802
Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 62774848 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 62774848 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  62774848 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  62774848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 1.otbn_stress_all_with_rand_reset.108331098541955709964764925600374622657259779308725068455912996631138794429820
    Line 218, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 539510783 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 539510783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.otbn_stress_all_with_rand_reset.18192090186234566748384219464369950928193799656254435096531464752484824476910
    Line 151, in log /nightly/runs/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 171767949 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 171767949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 2 failures:

Test otbn_escalate has 2 failures.

19.otbn_escalate.974687556197120556385660524425343936825561255820653625572540950816109910063
Line 113, in log /nightly/runs/scratch/master/otbn-sim-xcelium/19.otbn_escalate/latest/run.log

  UVM_FATAL @  57869482 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @  57869482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

52.otbn_escalate.113289381188694699331545650938065693996584012742789298394812850035195349021485
Line 101, in log /nightly/runs/scratch/master/otbn-sim-xcelium/52.otbn_escalate/latest/run.log

  UVM_FATAL @  42760479 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @  42760479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.93927705204853029505943723396040609798554548881909597351328136900110719204924
    Line 294, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 533967172 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 533967172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:486) [otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.100411762129459948648999047436059281155083816891525540358364602628181673240063
    Line 289, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 30196804745 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 30196804745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 14.otbn_escalate.24197924955048253958695491707519704456322153505272255445488948879411251732527
    Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/14.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 15036235 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  15036235 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  15036235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 18.otbn_passthru_mem_tl_intg_err.48026973362282958041428971932118911712884188572759402675128721971422977771199
    Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/18.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   4659627 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   4659627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```