ROM_CTRL/32KB Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.190s	138.560us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.040s	306.266us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.490s	174.222us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.640s	598.813us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.910s	539.375us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.030s	177.266us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.490s	174.222us	20	20	100.00
		rom_ctrl_csr_aliasing	9.910s	539.375us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.900s	174.962us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.720s	555.195us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.530s	320.078us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	30.470s	4.024ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.100s	311.916us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.920s	1.001ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.350s	937.693us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.350s	937.693us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.040s	306.266us	5	5	100.00
		rom_ctrl_csr_rw	7.490s	174.222us	20	20	100.00
		rom_ctrl_csr_aliasing	9.910s	539.375us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.040s	303.738us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.040s	306.266us	5	5	100.00
		rom_ctrl_csr_rw	7.490s	174.222us	20	20	100.00
		rom_ctrl_csr_aliasing	9.910s	539.375us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.040s	303.738us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.768m	5.320ms	17	20	85.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	29.230s	3.881ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.616m	3.070ms	5	5	100.00
		rom_ctrl_tl_intg_err	49.590s	445.650us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.616m	3.070ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.616m	3.070ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.768m	5.320ms	17	20	85.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.768m	5.320ms	17	20	85.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.768m	5.320ms	17	20	85.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.768m	5.320ms	17	20	85.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.768m	5.320ms	17	20	85.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.616m	3.070ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.616m	3.070ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.190s	138.560us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.190s	138.560us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.190s	138.560us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	49.590s	445.650us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.768m	5.320ms	17	20	85.00
		rom_ctrl_kmac_err_chk	9.100s	311.916us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.768m	5.320ms	17	20	85.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.768m	5.320ms	17	20	85.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.768m	5.320ms	17	20	85.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	29.230s	3.881ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.616m	3.070ms	5	5	100.00
V2S		TOTAL			62	65	95.38
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	9.027m	20.711ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			263	266	98.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.60	99.73	99.41	100.00	100.00	100.00	98.98	99.05

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.

    • 7.rom_ctrl_corrupt_sig_fatal_chk.112411589655371448046713699457725902567993178020783021715551057569846829286916
      Line 103, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1676382284 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1676382284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 12.rom_ctrl_corrupt_sig_fatal_chk.59786058370781631785745004427523466235801616272455847173219733373627639827987
      Line 98, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 915125133 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 915125133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.