ROM_CTRL/64KB Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	10.570s	962.946us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.100s	1.083ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.730s	3.020ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.500s	298.634us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.570s	1.584ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.200s	2.080ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.730s	3.020ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.570s	1.584ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.810s	4.156ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.460s	301.298us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.530s	1.112ms	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	52.480s	1.076ms	19	20	95.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	22.950s	3.144ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	16.540s	1.842ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.170s	300.825us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.170s	300.825us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.100s	1.083ms	5	5	100.00
		rom_ctrl_csr_rw	15.730s	3.020ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.570s	1.584ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.500s	3.342ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.100s	1.083ms	5	5	100.00
		rom_ctrl_csr_rw	15.730s	3.020ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.570s	1.584ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.500s	3.342ms	20	20	100.00
V2		TOTAL			113	114	99.12
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.026m	8.091ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	43.370s	1.576ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	6.191m	2.554ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.434m	3.105ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	6.191m	2.554ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	6.191m	2.554ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.026m	8.091ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.026m	8.091ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.026m	8.091ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.026m	8.091ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.026m	8.091ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	6.191m	2.554ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	6.191m	2.554ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	10.570s	962.946us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	10.570s	962.946us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	10.570s	962.946us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.434m	3.105ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.026m	8.091ms	20	20	100.00
		rom_ctrl_kmac_err_chk	22.950s	3.144ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.026m	8.091ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.026m	8.091ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.026m	8.091ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	43.370s	1.576ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	6.191m	2.554ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	9.265m	5.456ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			265	266	99.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.73	99.41	100.00	100.00	100.00	98.98	99.28

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:695) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire has 1 failures:
  • Test rom_ctrl_stress_all has 1 failures.

    • 11.rom_ctrl_stress_all.32666466185226815594052839635232667504707343436531077938499448055167177986951
      Line 74, in log /nightly/runs/scratch/master/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 2189249105 ps: (cip_base_vseq.sv:695) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 2189249105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---