RV_TIMER Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.950s	29.264us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.100s	45.876us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.190s	12.736us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.570s	800.873us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.220s	51.137us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.370s	24.788us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.190s	12.736us	20	20	100.00
		rv_timer_csr_aliasing	2.220s	51.137us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	14.000s	18.324ms	20	20	100.00
V2	disabled	rv_timer_disabled	6.620s	3.736ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	11.958m	3.123s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	11.958m	3.123s	10	10	100.00
V2	stress	rv_timer_stress_all	6.980s	6.300ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.160s	12.689us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.050s	11.998us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.660s	159.028us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.660s	159.028us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.100s	45.876us	5	5	100.00
		rv_timer_csr_rw	2.190s	12.736us	20	20	100.00
		rv_timer_csr_aliasing	2.220s	51.137us	5	5	100.00
		rv_timer_same_csr_outstanding	2.310s	35.616us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.100s	45.876us	5	5	100.00
		rv_timer_csr_rw	2.190s	12.736us	20	20	100.00
		rv_timer_csr_aliasing	2.220s	51.137us	5	5	100.00
		rv_timer_same_csr_outstanding	2.310s	35.616us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.430s	2.046ms	5	5	100.00
		rv_timer_tl_intg_err	2.770s	223.853us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.770s	223.853us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.960s	101.169us	10	10	100.00
V3	max_value	rv_timer_max	2.010s	24.078us	10	10	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	52.300s	10.149ms	20	20	100.00
V3		TOTAL			40	40	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.39	100.00	100.00	78.66	--	100.00	100.00	99.71