SPI_DEVICE/1R1W Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.303m	262.028ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.580s	41.426us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.920s	73.299us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.730s	5.485ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.690s	4.564ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.650s	106.103us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.920s	73.299us	20	20	100.00
		spi_device_csr_aliasing	17.690s	4.564ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.290s	18.857us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.120s	26.124us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.360s	16.521us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.290s	1.445us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	2.090s	8.749us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	8.240s	835.880us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.240s	835.880us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	48.520s	11.081ms	50	50	100.00
		spi_device_tpm_sts_read	2.750s	938.504us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.930s	31.837ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	29.150s	33.602ms	50	50	100.00
		spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	46.690s	23.977ms	50	50	100.00
		spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	46.690s	23.977ms	50	50	100.00
		spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	25.770s	10.695ms	50	50	100.00
		spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	25.770s	10.695ms	50	50	100.00
		spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	25.770s	10.695ms	50	50	100.00
		spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	25.770s	10.695ms	50	50	100.00
		spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	25.770s	10.695ms	50	50	100.00
		spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	38.590s	11.414ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.336m	99.402ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.336m	99.402ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.336m	99.402ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	51.510s	62.968ms	50	50	100.00
		spi_device_read_buffer_direct	19.920s	1.608ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.336m	99.402ms	50	50	100.00
		spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.449m	51.245ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	22.040s	2.684ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	22.040s	2.684ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.303m	262.028ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.997m	64.322ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.733m	750.624ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.400s	27.495us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.370s	16.755us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.840s	300.457us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.840s	300.457us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.580s	41.426us	5	5	100.00
		spi_device_csr_rw	3.920s	73.299us	20	20	100.00
		spi_device_csr_aliasing	17.690s	4.564ms	5	5	100.00
		spi_device_same_csr_outstanding	4.610s	744.878us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.580s	41.426us	5	5	100.00
		spi_device_csr_rw	3.920s	73.299us	20	20	100.00
		spi_device_csr_aliasing	17.690s	4.564ms	5	5	100.00
		spi_device_same_csr_outstanding	4.610s	744.878us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.870s	204.907us	5	5	100.00
		spi_device_tl_intg_err	17.930s	2.043ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.930s	2.043ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.336m	111.190ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.80	99.11	96.50	71.19	89.36	98.39	95.76	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.95219893460461675936310397551322407096947611387896819079965212708458613231511
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   5747253 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[11])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   5747253 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   5747253 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[907])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.52240905001836565620973689117637426928952760504946109652121698799408434108561
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4165736 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[66])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4165736 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4165736 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[962])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.79078760537769202268379365720109109673842878043260759012530746864417712195384
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   6179602 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2476fa [1001000111011011111010] vs 0x0 [0])
        UVM_ERROR @   6204602 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xac924d [101011001001001001001101] vs 0x0 [0])
        UVM_ERROR @   6260602 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xba7558 [101110100111010101011000] vs 0x0 [0])
        UVM_ERROR @   6261602 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x91ee7e [100100011110111001111110] vs 0x0 [0])
        UVM_ERROR @   6272602 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd55cdc [110101010101110011011100] vs 0x0 [0])