SPI_HOST Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.967m	10.857ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	62.802us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	6.000s	19.474us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	474.850us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	107.493us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	52.362us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	6.000s	19.474us	20	20	100.00
		spi_host_csr_aliasing	5.000s	107.493us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	17.352us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	25.280us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	38.000s	63.615us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	39.000s	81.978us	50	50	100.00
		spi_host_error_cmd	38.000s	81.483us	50	50	100.00
		spi_host_event	9.783m	38.133ms	50	50	100.00
V2	clock_rate	spi_host_speed	41.000s	529.195us	50	50	100.00
V2	speed	spi_host_speed	41.000s	529.195us	50	50	100.00
V2	chip_select_timing	spi_host_speed	41.000s	529.195us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	2.417m	6.690ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	38.000s	42.395us	50	50	100.00
V2	cpol_cpha	spi_host_speed	41.000s	529.195us	50	50	100.00
V2	full_cycle	spi_host_speed	41.000s	529.195us	50	50	100.00
V2	duplex	spi_host_smoke	1.967m	10.857ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.967m	10.857ms	50	50	100.00
V2	stress_all	spi_host_stress_all	34.383m	1.000s	48	50	96.00
V2	spien	spi_host_spien	2.017m	9.113ms	50	50	100.00
V2	stall	spi_host_status_stall	16.200m	78.811ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	39.000s	371.552us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	39.000s	81.978us	50	50	100.00
V2	alert_test	spi_host_alert_test	38.000s	39.274us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	57.605us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	186.031us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	186.031us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	62.802us	5	5	100.00
		spi_host_csr_rw	6.000s	19.474us	20	20	100.00
		spi_host_csr_aliasing	5.000s	107.493us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	31.589us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	62.802us	5	5	100.00
		spi_host_csr_rw	6.000s	19.474us	20	20	100.00
		spi_host_csr_aliasing	5.000s	107.493us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	31.589us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	152.772us	20	20	100.00
		spi_host_sec_cm	37.000s	293.405us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	152.772us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	11.717m	50.006ms	7	10	70.00
		TOTAL			835	840	99.40

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.20	96.78	93.27	98.69	94.36	73.07	100.00	97.29	90.42

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

  • Test spi_host_upper_range_clkdiv has 2 failures.

    • 0.spi_host_upper_range_clkdiv.79867500018291985973133038172807883681877215807099535243509604132134544687822
      Line 124, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.spi_host_upper_range_clkdiv.100553697140006788262041312813694963599383896073489736892489704737031123989175
      Line 112, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_stress_all has 2 failures.

    • 8.spi_host_stress_all.25751714207088761267300680973618203785608579426410758737726111682743648704316
      Line 319, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/8.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 40.spi_host_stress_all.79375867259210674146159410846006247009609052928524095131606332656789068402910
      Line 126, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/40.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 1.spi_host_upper_range_clkdiv.108659118266544665066790404481888649273739531679982382158116598785464422952732
      Line 146, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 50005986583 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 50000000ns spi_host_reg_block.status.active (addr=0x80cbc294, Comparison=CompareOpEq, exp_data=0x0, call_count=15
        UVM_INFO @ 50005986583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---