SRAM_CTRL/MAIN Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.503m	1.324ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.400s	14.547us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.280s	24.877us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.620s	172.660us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.340s	22.893us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.120s	735.011us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.280s	24.877us	20	20	100.00
		sram_ctrl_csr_aliasing	2.340s	22.893us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.107m	153.851ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.257m	23.155ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	23.022m	176.318ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.674m	6.796ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	38.092m	33.174ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.941m	29.307ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.322m	174.958ms	50	50	100.00
V2	executable	sram_ctrl_executable	19.797m	52.511ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.827m	1.940ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.207m	281.586ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.623m	1.601ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.646m	1.692ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.843m	2.587ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.608m	11.692ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.660s	1.765ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.552h	431.546ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.230s	27.814us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.390s	689.506us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.390s	689.506us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.400s	14.547us	5	5	100.00
		sram_ctrl_csr_rw	2.280s	24.877us	20	20	100.00
		sram_ctrl_csr_aliasing	2.340s	22.893us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.360s	39.665us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.400s	14.547us	5	5	100.00
		sram_ctrl_csr_rw	2.280s	24.877us	20	20	100.00
		sram_ctrl_csr_aliasing	2.340s	22.893us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.360s	39.665us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.215m	30.685ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.120s	4.339us	0	5	0.00
		sram_ctrl_tl_intg_err	4.150s	261.541us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.120s	4.339us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.150s	261.541us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.608m	11.692ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	25.608m	11.692ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.280s	24.877us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	19.797m	52.511ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	19.797m	52.511ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	19.797m	52.511ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.322m	174.958ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.790s	4.763ms	41	50	82.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.215m	30.685ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.290s	9.436ms	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.503m	1.324ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.503m	1.324ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	19.797m	52.511ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.120s	4.339us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.322m	174.958ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.120s	4.339us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.120s	4.339us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.503m	1.324ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.120s	4.339us	0	5	0.00
V2S		TOTAL			120	145	82.76
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.125m	9.854ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1165	1190	97.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.11	93.01	85.18	100.00	98.03	98.61	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:
  • Test sram_ctrl_readback_err has 11 failures.

    • 0.sram_ctrl_readback_err.91407744212742861250843729076340511832715363054585232482638970072222656961146
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1342122064 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x74) != exp (0xd)
        UVM_INFO @ 1342122064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_readback_err.73982364296697379217152971053694944416475764341989463326388365134641911191367
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 675748762 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x40) != exp (0x3e)
        UVM_INFO @ 675748762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• Offending 'reqfifo_rvalid' has 9 failures:
  • Test sram_ctrl_mubi_enc_err has 9 failures.

    • 0.sram_ctrl_mubi_enc_err.10701670904220558497541833799316080350198637902867535645368404639669675294553
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 675658877 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 675658877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.sram_ctrl_mubi_enc_err.13525907465226878414133775661895067232699543723613946567064477411976906917628
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 717714749 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 717714749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 5 failures:
  • Test sram_ctrl_sec_cm has 5 failures.

    • 0.sram_ctrl_sec_cm.17553268793797656433249309185824831917499860606388792180966136748997280692357
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4339438 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4339438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.22138294891524148867859041853956597112034189032721428928195669281462466207719
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7101111 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7101111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.