SRAM_CTRL/RET Simulation Results

Friday June 13 2025 17:37:55 UTC

GitHub Revision: 2211fb0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.721m	1.246ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.080s	20.271us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.080s	12.097us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.500s	293.166us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.200s	17.821us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.070s	277.210us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.080s	12.097us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	17.821us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.170s	2.267ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.250s	208.786us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	22.478m	20.180ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.061m	15.817ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.419m	19.073ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	19.584m	9.611ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.240s	3.653ms	50	50	100.00
V2	executable	sram_ctrl_executable	19.571m	7.204ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.734m	6.222ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.484m	118.992ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.704m	273.542us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.535m	1.484ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.617m	285.407us	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.723m	156.729ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.300s	29.516us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.454h	334.017ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.170s	36.563us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.570s	531.593us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.570s	531.593us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.080s	20.271us	5	5	100.00
		sram_ctrl_csr_rw	2.080s	12.097us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	17.821us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.190s	145.567us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.080s	20.271us	5	5	100.00
		sram_ctrl_csr_rw	2.080s	12.097us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	17.821us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.190s	145.567us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.610s	2.821ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.960s	1.231us	0	5	0.00
		sram_ctrl_tl_intg_err	3.900s	440.166us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.960s	1.231us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.900s	440.166us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.723m	156.729ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	27.723m	156.729ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.080s	12.097us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	19.571m	7.204ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	19.571m	7.204ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	19.571m	7.204ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.240s	3.653ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.640s	364.029us	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.610s	2.821ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.660s	324.800us	34	50	68.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.721m	1.246ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.721m	1.246ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	19.571m	7.204ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.960s	1.231us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.240s	3.653ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.960s	1.231us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.960s	1.231us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.721m	1.246ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.960s	1.231us	0	5	0.00
V2S		TOTAL			120	145	82.76
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.176m	13.009ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1164	1190	97.82

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	99.07	93.01	85.10	100.00	97.99	98.60	98.14

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 16 failures:

  • Test sram_ctrl_readback_err has 16 failures.

    • 0.sram_ctrl_readback_err.23251228301288518995291718943530191248121089704752554916995591102329422411014
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 143801163 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x58) != exp (0x30)
        UVM_INFO @ 143801163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_readback_err.108265813177626191361287946826763096355211190956493836871982039643758063808751
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 324800038 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x52)
        UVM_INFO @ 324800038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 14 more failures.

• Offending 'reqfifo_rvalid' has 4 failures:

  • Test sram_ctrl_mubi_enc_err has 4 failures.

    • 4.sram_ctrl_mubi_enc_err.105568731811374001226739309756909502517080253508996268038788153365865034526855
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  25103905 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  25103905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.sram_ctrl_mubi_enc_err.5072844533879095155484439795449690373962435823692387983909087523838965456817
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 106824873 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 106824873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.111672138414907500468268666159121038536104248494679017203965078261599611838067
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7320824 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7320824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.15627668360405656853810729597009810262917567288207805690091433130985028516172
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7686900 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7686900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 1.sram_ctrl_sec_cm.44366113352708437031100113876314173105669632054713309364336954486462164261206
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @    878571 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @    878571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.28707649945669553457501635229307784067551701481632918660994527088005618939346
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1230530 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1230530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.69679679249899606854411559650784240579067766777509840053492144605990146909943
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   6964277 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   6964277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 16.sram_ctrl_csr_mem_rw_with_rand_reset.47094139608276002100010969943003941938018159821008219756534530366021804295608
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  96876913 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  96876913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---