2211fb0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 29.710s | 5.888ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | uart_csr_hw_reset | 2.220s | 129.572us | 5 | 5 | 100.00 |
| V1 | csr_rw | uart_csr_rw | 2.350s | 27.514us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | uart_csr_bit_bash | 3.840s | 1.001ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | uart_csr_aliasing | 2.450s | 19.802us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 2.700s | 32.874us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 2.350s | 27.514us | 20 | 20 | 100.00 |
| uart_csr_aliasing | 2.450s | 19.802us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | base_random_seq | uart_tx_rx | 3.459m | 93.016ms | 50 | 50 | 100.00 |
| V2 | parity | uart_smoke | 29.710s | 5.888ms | 50 | 50 | 100.00 |
| uart_tx_rx | 3.459m | 93.016ms | 50 | 50 | 100.00 | ||
| V2 | parity_error | uart_intr | 10.323m | 490.747ms | 49 | 50 | 98.00 |
| uart_rx_parity_err | 5.826m | 169.003ms | 50 | 50 | 100.00 | ||
| V2 | watermark | uart_tx_rx | 3.459m | 93.016ms | 50 | 50 | 100.00 |
| uart_intr | 10.323m | 490.747ms | 49 | 50 | 98.00 | ||
| V2 | fifo_full | uart_fifo_full | 8.220m | 160.393ms | 50 | 50 | 100.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 11.959m | 164.065ms | 50 | 50 | 100.00 |
| V2 | fifo_reset | uart_fifo_reset | 5.420m | 110.450ms | 300 | 300 | 100.00 |
| V2 | rx_frame_err | uart_intr | 10.323m | 490.747ms | 49 | 50 | 98.00 |
| V2 | rx_break_err | uart_intr | 10.323m | 490.747ms | 49 | 50 | 98.00 |
| V2 | rx_timeout | uart_intr | 10.323m | 490.747ms | 49 | 50 | 98.00 |
| V2 | perf | uart_perf | 22.665m | 28.491ms | 48 | 50 | 96.00 |
| V2 | sys_loopback | uart_loopback | 24.960s | 8.774ms | 50 | 50 | 100.00 |
| V2 | line_loopback | uart_loopback | 24.960s | 8.774ms | 50 | 50 | 100.00 |
| V2 | rx_noise_filter | uart_noise_filter | 2.700m | 152.858ms | 7 | 50 | 14.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 1.161m | 47.753ms | 50 | 50 | 100.00 |
| V2 | tx_overide | uart_tx_ovrd | 22.940s | 6.700ms | 50 | 50 | 100.00 |
| V2 | rx_oversample | uart_rx_oversample | 1.050m | 6.180ms | 50 | 50 | 100.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 17.767m | 169.294ms | 49 | 50 | 98.00 |
| V2 | stress_all | uart_stress_all | 22.913m | 605.491ms | 41 | 50 | 82.00 |
| V2 | alert_test | uart_alert_test | 2.240s | 62.367us | 50 | 50 | 100.00 |
| V2 | intr_test | uart_intr_test | 2.270s | 121.286us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 4.010s | 169.357us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | uart_tl_errors | 4.010s | 169.357us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 2.220s | 129.572us | 5 | 5 | 100.00 |
| uart_csr_rw | 2.350s | 27.514us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 2.450s | 19.802us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 2.480s | 42.206us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 2.220s | 129.572us | 5 | 5 | 100.00 |
| uart_csr_rw | 2.350s | 27.514us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 2.450s | 19.802us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 2.480s | 42.206us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1034 | 1090 | 94.86 | |||
| V2S | tl_intg_err | uart_sec_cm | 2.380s | 253.969us | 5 | 5 | 100.00 |
| uart_tl_intg_err | 3.200s | 198.848us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 3.200s | 198.848us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | uart_stress_all_with_rand_reset | 1.602m | 17.597ms | 85 | 100 | 85.00 |
| V3 | TOTAL | 85 | 100 | 85.00 | |||
| TOTAL | 1249 | 1320 | 94.62 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.01 | 99.48 | 98.25 | 74.67 | -- | 98.14 | 100.00 | 99.50 |
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 29 failures:
1.uart_noise_filter.95866180596346247335176498561699645026088357357283735681308679746647121660772
Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log
UVM_ERROR @ 2597132513 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2597132513 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 2656860724 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 2759213253 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (42 [0x2a] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2981626361 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
2.uart_noise_filter.103757484648961370324597068337711291886321196418049655457682353822028229976409
Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log
UVM_ERROR @ 1741994807 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1741994807 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 2888396843 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 3081010199 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR @ 3236851352 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
... and 16 more failures.
10.uart_stress_all.42243465249013638154667120541273138001130159642050368825340315436416408634603
Line 107, in log /nightly/runs/scratch/master/uart-sim-vcs/10.uart_stress_all/latest/run.log
UVM_ERROR @ 257857841340 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 257857841340 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 259942483017 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 259942483017 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 260984324685 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
25.uart_stress_all.71409287332577733548785245681210306384334205106463682310308317103691144654703
Line 98, in log /nightly/runs/scratch/master/uart-sim-vcs/25.uart_stress_all/latest/run.log
UVM_ERROR @ 169867720032 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 170032632086 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 170032632086 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 170033545124 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 170033545124 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
... and 3 more failures.
18.uart_stress_all_with_rand_reset.108582792143651626132118625124325811536173392546571667916964615514108474698917
Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28886685 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 641086685 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 641086685 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 641086685 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 764886685 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5, clk_pulses: 0
36.uart_stress_all_with_rand_reset.38826822455984336938146549929390896519894892421546376741888725719015554867943
Line 132, in log /nightly/runs/scratch/master/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1241208342 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1241867898 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1242527454 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1243187010 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1243846566 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
... and 4 more failures.
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 21 failures:
5.uart_noise_filter.31222390021141719984324320473243669885934025611994568137016067788003819820731
Line 71, in log /nightly/runs/scratch/master/uart-sim-vcs/5.uart_noise_filter/latest/run.log
UVM_ERROR @ 2408273282 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 2408293282 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2408313282 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (91 [0x5b] vs 252 [0xfc]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2408333282 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2408353282 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (91 [0x5b] vs 255 [0xff]) reg name: uart_reg_block.rdata
11.uart_noise_filter.82934444676179199174996724888102122406861582254804842652125000138432396225287
Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/11.uart_noise_filter/latest/run.log
UVM_ERROR @ 2263268229 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 2263278229 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2263288229 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (176 [0xb0] vs 119 [0x77]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2399468229 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 2399468229 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
... and 13 more failures.
26.uart_stress_all.89999225588782727041303330190591838067256988013995192046788695865446941017476
Line 81, in log /nightly/runs/scratch/master/uart-sim-vcs/26.uart_stress_all/latest/run.log
UVM_ERROR @ 46511003723 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4, clk_pulses: 0
UVM_ERROR @ 46511015217 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 46511026711 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (135 [0x87] vs 237 [0xed]) reg name: uart_reg_block.rdata
UVM_ERROR @ 46511038205 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 46511049699 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (135 [0x87] vs 247 [0xf7]) reg name: uart_reg_block.rdata
29.uart_stress_all.94775181157931627824141986282920230700203839821787363414628361468032931138748
Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/29.uart_stress_all/latest/run.log
UVM_ERROR @ 203345071 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 203355071 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 203365071 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 203375071 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 203385071 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata
... and 1 more failures.
62.uart_stress_all_with_rand_reset.65512385441832155035479642872813934293396903392051481884423379736490781955673
Line 223, in log /nightly/runs/scratch/master/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 66235984308 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 66236109308 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 66236234308 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (123 [0x7b] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_INFO @ 66514984308 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/879
UVM_ERROR @ 66661109308 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
64.uart_stress_all_with_rand_reset.6136416676648476461738397497877856754527956799183985315795413600726494942279
Line 125, in log /nightly/runs/scratch/master/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7758450042 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7, clk_pulses: 0
UVM_ERROR @ 7758490042 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 7758890042 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (241 [0xf1] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 7758930042 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 7759090042 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (241 [0xf1] vs 245 [0xf5]) reg name: uart_reg_block.rdata
... and 1 more failures.
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 9 failures:
4.uart_noise_filter.83357469419490552634907970665966880541257409999368988423672558496010637869871
Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log
UVM_ERROR @ 1627881028 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 1627881028 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1627881028 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1659881028 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 3
UVM_ERROR @ 1659891028 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
13.uart_noise_filter.67459560382954860130964713403230742760069182888152685839313622661207027107346
Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/13.uart_noise_filter/latest/run.log
UVM_ERROR @ 15614463484 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 15614463484 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 15614463484 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 16021258405 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 17, clk_pulses: 0
UVM_ERROR @ 16021341739 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (161 [0xa1] vs 253 [0xfd]) reg name: uart_reg_block.rdata
... and 6 more failures.
43.uart_stress_all.49956857824967982306504942413883699309067316582533040538274707952282575075341
Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/43.uart_stress_all/latest/run.log
UVM_ERROR @ 174818878 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 174818878 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 298871359 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 298871359 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 298871359 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 4 failures:
Test uart_stress_all_with_rand_reset has 1 failures.
16.uart_stress_all_with_rand_reset.59166594835851612318996618145165660394552335452290205959744666174203540852710
Line 210, in log /nightly/runs/scratch/master/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18414881108 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_ERROR @ 18414881108 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
UVM_INFO @ 18536352978 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 9/10
UVM_INFO @ 18536495835 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Test uart_long_xfer_wo_dly has 1 failures.
20.uart_long_xfer_wo_dly.34418377347780537554765549428417010604084272204434786314960025007560243524309
Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest/run.log
UVM_ERROR @ 1206554 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 3833869770 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/5
UVM_INFO @ 10034968199 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/5
UVM_INFO @ 20072933734 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/5
UVM_INFO @ 27451864498 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/5
Test uart_perf has 2 failures.
31.uart_perf.92967326893157071756818226282313519426347960762854652392820503732621338530402
Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/31.uart_perf/latest/run.log
UVM_ERROR @ 4885212146 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 10524495811 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/9
UVM_INFO @ 16180370551 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/9
UVM_INFO @ 18380801646 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/9
UVM_INFO @ 19474847337 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/9
34.uart_perf.90044613655698216138811309977474749367568462790534733699301085553935676973576
Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/34.uart_perf/latest/run.log
UVM_ERROR @ 1008183 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_ERROR @ 1008183 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
UVM_INFO @ 698585959 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/10
UVM_INFO @ 699237291 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/10
UVM_INFO @ 7652579623 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/10
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 2 failures:
Test uart_stress_all_with_rand_reset has 1 failures.
3.uart_stress_all_with_rand_reset.110125997607247229119906730731512348180677069029817134664951008400538680650342
Line 160, in log /nightly/runs/scratch/master/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3472139339 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 3474019339 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 3476039339 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 3476599339 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 3476599339 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
Test uart_noise_filter has 1 failures.
8.uart_noise_filter.44941584629971660273130490885028680523567009355488086794786181381313526912397
Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log
UVM_ERROR @ 388583713 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 425174183 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 425196910 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 425219637 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 425242364 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (cip_base_vseq.sv:928) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
5.uart_stress_all_with_rand_reset.24730531238050958209220353843440714413175004851419408491721204275239775022976
Line 97, in log /nightly/runs/scratch/master/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1466264761 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1466265581 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1466265581 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 1466284761 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1
99.uart_stress_all_with_rand_reset.46988255621837350694657233500390962189225303502258139983858870003451761650134
Line 79, in log /nightly/runs/scratch/master/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 115058252 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 115060206 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 115060206 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 115068669 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:
Test uart_stress_all_with_rand_reset has 1 failures.
26.uart_stress_all_with_rand_reset.66991415284062811479575291193758909043314400988761145080837029861279189710918
Line 120, in log /nightly/runs/scratch/master/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1759338947 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 1763738947 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1763738947 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1819278947 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR @ 1819298947 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
Test uart_noise_filter has 1 failures.
28.uart_noise_filter.58367237903524146349227339229093837816875600513052005641157236701565405199474
Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/28.uart_noise_filter/latest/run.log
UVM_ERROR @ 65286992 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 65286992 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 70506992 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 70506992 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 114396992 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxDone has 1 failures:
13.uart_intr.20654605913523229984429515866325278779923658856458131299085888035849482809497
Line 96, in log /nightly/runs/scratch/master/uart-sim-vcs/13.uart_intr/latest/run.log
UVM_ERROR @ 17635261333 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxDone
UVM_ERROR @ 17635261333 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxDone
UVM_INFO @ 17638928007 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Testing RxWatermark
UVM_INFO @ 18383096162 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
UVM_ERROR (cip_base_vseq.sv:832) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
78.uart_stress_all_with_rand_reset.21646862067399660454260743987725059278247307155924997342017950767360426195776
Line 84, in log /nightly/runs/scratch/master/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 685490670 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 685490670 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 685674342 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Stress w/ reset is done for run 1/10