AES/MASKED Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	60.094us	1	1	100.00
V1	smoke	aes_smoke	8.000s	321.445us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	57.625us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	66.321us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.342ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	568.462us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	119.146us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	66.321us	20	20	100.00
		aes_csr_aliasing	8.000s	568.462us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	321.445us	50	50	100.00
		aes_config_error	19.000s	2.270ms	50	50	100.00
		aes_stress	42.000s	2.552ms	50	50	100.00
V2	key_length	aes_smoke	8.000s	321.445us	50	50	100.00
		aes_config_error	19.000s	2.270ms	50	50	100.00
		aes_stress	42.000s	2.552ms	50	50	100.00
V2	back2back	aes_stress	42.000s	2.552ms	50	50	100.00
		aes_b2b	27.000s	456.434us	50	50	100.00
V2	backpressure	aes_stress	42.000s	2.552ms	50	50	100.00
V2	multi_message	aes_smoke	8.000s	321.445us	50	50	100.00
		aes_config_error	19.000s	2.270ms	50	50	100.00
		aes_stress	42.000s	2.552ms	50	50	100.00
		aes_alert_reset	16.000s	622.013us	49	50	98.00
V2	failure_test	aes_man_cfg_err	8.000s	738.419us	50	50	100.00
		aes_config_error	19.000s	2.270ms	50	50	100.00
		aes_alert_reset	16.000s	622.013us	49	50	98.00
V2	trigger_clear_test	aes_clear	13.000s	171.660us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	383.640us	1	1	100.00
V2	reset_recovery	aes_alert_reset	16.000s	622.013us	49	50	98.00
V2	stress	aes_stress	42.000s	2.552ms	50	50	100.00
V2	sideload	aes_stress	42.000s	2.552ms	50	50	100.00
		aes_sideload	8.000s	380.295us	50	50	100.00
V2	deinitialization	aes_deinit	7.000s	99.250us	50	50	100.00
V2	stress_all	aes_stress_all	3.333m	17.929ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	83.882us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	182.832us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	182.832us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	57.625us	5	5	100.00
		aes_csr_rw	5.000s	66.321us	20	20	100.00
		aes_csr_aliasing	8.000s	568.462us	5	5	100.00
		aes_same_csr_outstanding	6.000s	103.155us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	57.625us	5	5	100.00
		aes_csr_rw	5.000s	66.321us	20	20	100.00
		aes_csr_aliasing	8.000s	568.462us	5	5	100.00
		aes_same_csr_outstanding	6.000s	103.155us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	19.000s	1.077ms	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	982.029us	48	50	96.00
		aes_control_fi	47.000s	10.006ms	281	300	93.67
		aes_cipher_fi	44.000s	10.012ms	342	350	97.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	314.780us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	314.780us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	314.780us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	314.780us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	452.987us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	804.382us	5	5	100.00
		aes_tl_intg_err	7.000s	549.072us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	549.072us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	16.000s	622.013us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	314.780us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	321.445us	50	50	100.00
		aes_stress	42.000s	2.552ms	50	50	100.00
		aes_alert_reset	16.000s	622.013us	49	50	98.00
		aes_core_fi	42.000s	10.005ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	314.780us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	294.968us	50	50	100.00
		aes_stress	42.000s	2.552ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	42.000s	2.552ms	50	50	100.00
		aes_sideload	8.000s	380.295us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	294.968us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	294.968us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	294.968us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	294.968us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	294.968us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	42.000s	2.552ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	42.000s	2.552ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	982.029us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	982.029us	48	50	96.00
		aes_control_fi	47.000s	10.006ms	281	300	93.67
		aes_cipher_fi	44.000s	10.012ms	342	350	97.71
		aes_ctr_fi	11.000s	654.313us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	982.029us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	982.029us	48	50	96.00
		aes_control_fi	47.000s	10.006ms	281	300	93.67
		aes_cipher_fi	44.000s	10.012ms	342	350	97.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	44.000s	10.012ms	342	350	97.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	982.029us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	982.029us	48	50	96.00
		aes_control_fi	47.000s	10.006ms	281	300	93.67
		aes_ctr_fi	11.000s	654.313us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	982.029us	48	50	96.00
		aes_control_fi	47.000s	10.006ms	281	300	93.67
		aes_cipher_fi	44.000s	10.012ms	342	350	97.71
		aes_ctr_fi	11.000s	654.313us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	16.000s	622.013us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	982.029us	48	50	96.00
		aes_control_fi	47.000s	10.006ms	281	300	93.67
		aes_cipher_fi	44.000s	10.012ms	342	350	97.71
		aes_ctr_fi	11.000s	654.313us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	982.029us	48	50	96.00
		aes_control_fi	47.000s	10.006ms	281	300	93.67
		aes_cipher_fi	44.000s	10.012ms	342	350	97.71
		aes_ctr_fi	11.000s	654.313us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	982.029us	48	50	96.00
		aes_control_fi	47.000s	10.006ms	281	300	93.67
		aes_ctr_fi	11.000s	654.313us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	982.029us	48	50	96.00
		aes_control_fi	47.000s	10.006ms	281	300	93.67
		aes_cipher_fi	44.000s	10.012ms	342	350	97.71
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	25.000s	463.321us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1559	1602	97.32

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.59	96.43	99.40	95.58	97.99	97.78	99.11	99.20

Failure Buckets

Job timed out after * minutes has 15 failures:
- Test aes_control_fi has 14 failures.
  - 21.aes_control_fi.54613510006500807725383995907169703064880396234801891521286373737527662700022
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 39.aes_control_fi.6895168061711153794063873426336697076690085590648983903203705466298109571967
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 1 failures.
  - 284.aes_cipher_fi.51096023243079078942323432020218734124663140231065849483526411293192764928507
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/284.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 21.aes_cipher_fi.60581469536106126715536281833146055956997604153945556267441933896400718517267
    Line 148, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006606001 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006606001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 84.aes_cipher_fi.57954337319594465301484840840200832566577898303382542633499076562523965088901
    Line 134, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/84.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011696039 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011696039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.63281943936564232388119807079697272391585484334750467744895675791139593775485
Line 500, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1863488928 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1863488928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.86654826017858151971227972491578815747761105115741226935565853419926479834207
Line 473, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 251277951 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 251277951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 10.aes_control_fi.78275367666437633883942082256137845008573962623167376258045472868531990048456
    Line 148, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021845555 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021845555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 35.aes_control_fi.100366440639519851044969282679346795873603819860333939389805038261042472895166
    Line 136, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015499083 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015499083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 2.aes_stress_all_with_rand_reset.80292992934780954230386434216838183979359126734133458145612514543534212343730
    Line 132, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   9611069 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @   9611069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_stress_all_with_rand_reset.52323393942168192062808462761087191486425750358675228777401079294692977871074
    Line 600, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4184817070 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 4184817070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 7.aes_core_fi.23680067092191246807362678565996535133544246811275895067295035595291142714236
    Line 140, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10072289745 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10072289745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 34.aes_core_fi.18285491106411624194379964070610535310354528618701830293936683353684329496199
    Line 134, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005059779 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005059779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 1 failures.

5.aes_fi.76447953246412433707606472689166215963183814175958227716222922545101039682620
Line 2814, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 15252060 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 15230783 PS)
  UVM_ERROR @  15252060 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  15252060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_alert_reset has 1 failures.

29.aes_alert_reset.8620651380700358430085917270117981809013572582858791155406326223053256155566
Line 1017, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/29.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 11836981 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 11825353 PS)
  UVM_ERROR @  11836981 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  11836981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.23632797863973602383068579681335751591737525546790411676612496783602377725231
    Line 131, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  30580315 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  30580315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

22.aes_fi.66223055871384828386599432507919526061804644211833110200584763921140044300920
Line 1357, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/22.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 7819899 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 7799899 PS)
  UVM_ERROR @   7819899 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   7819899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---