AES/UNMASKED Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	98.245us	1	1	100.00
V1	smoke	aes_smoke	7.000s	842.612us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	123.818us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	132.439us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1.784ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	118.687us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	229.702us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	132.439us	20	20	100.00
		aes_csr_aliasing	8.000s	118.687us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	842.612us	50	50	100.00
		aes_config_error	7.000s	230.843us	50	50	100.00
		aes_stress	6.000s	64.963us	50	50	100.00
V2	key_length	aes_smoke	7.000s	842.612us	50	50	100.00
		aes_config_error	7.000s	230.843us	50	50	100.00
		aes_stress	6.000s	64.963us	50	50	100.00
V2	back2back	aes_stress	6.000s	64.963us	50	50	100.00
		aes_b2b	9.000s	422.037us	50	50	100.00
V2	backpressure	aes_stress	6.000s	64.963us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	842.612us	50	50	100.00
		aes_config_error	7.000s	230.843us	50	50	100.00
		aes_stress	6.000s	64.963us	50	50	100.00
		aes_alert_reset	7.000s	108.588us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	77.120us	50	50	100.00
		aes_config_error	7.000s	230.843us	50	50	100.00
		aes_alert_reset	7.000s	108.588us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	377.677us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	253.337us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	108.588us	50	50	100.00
V2	stress	aes_stress	6.000s	64.963us	50	50	100.00
V2	sideload	aes_stress	6.000s	64.963us	50	50	100.00
		aes_sideload	6.000s	93.161us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	198.816us	50	50	100.00
V2	stress_all	aes_stress_all	28.000s	1.527ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	51.365us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	89.452us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	89.452us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	123.818us	5	5	100.00
		aes_csr_rw	8.000s	132.439us	20	20	100.00
		aes_csr_aliasing	8.000s	118.687us	5	5	100.00
		aes_same_csr_outstanding	7.000s	63.854us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	123.818us	5	5	100.00
		aes_csr_rw	8.000s	132.439us	20	20	100.00
		aes_csr_aliasing	8.000s	118.687us	5	5	100.00
		aes_same_csr_outstanding	7.000s	63.854us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	8.000s	197.441us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	112.478us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	279	300	93.00
		aes_cipher_fi	27.000s	10.010ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	119.543us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	119.543us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	119.543us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	119.543us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	10.000s	146.452us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	968.167us	5	5	100.00
		aes_tl_intg_err	10.000s	170.204us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	170.204us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	108.588us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	119.543us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	842.612us	50	50	100.00
		aes_stress	6.000s	64.963us	50	50	100.00
		aes_alert_reset	7.000s	108.588us	50	50	100.00
		aes_core_fi	26.000s	10.004ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	119.543us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	71.285us	50	50	100.00
		aes_stress	6.000s	64.963us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	64.963us	50	50	100.00
		aes_sideload	6.000s	93.161us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	71.285us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	71.285us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	71.285us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	71.285us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	71.285us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	64.963us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	64.963us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	112.478us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	112.478us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	279	300	93.00
		aes_cipher_fi	27.000s	10.010ms	324	350	92.57
		aes_ctr_fi	6.000s	63.001us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	112.478us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	112.478us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	279	300	93.00
		aes_cipher_fi	27.000s	10.010ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	27.000s	10.010ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	112.478us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	112.478us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	279	300	93.00
		aes_ctr_fi	6.000s	63.001us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	112.478us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	279	300	93.00
		aes_cipher_fi	27.000s	10.010ms	324	350	92.57
		aes_ctr_fi	6.000s	63.001us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	108.588us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	112.478us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	279	300	93.00
		aes_cipher_fi	27.000s	10.010ms	324	350	92.57
		aes_ctr_fi	6.000s	63.001us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	112.478us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	279	300	93.00
		aes_cipher_fi	27.000s	10.010ms	324	350	92.57
		aes_ctr_fi	6.000s	63.001us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	112.478us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	279	300	93.00
		aes_ctr_fi	6.000s	63.001us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	112.478us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	279	300	93.00
		aes_cipher_fi	27.000s	10.010ms	324	350	92.57
V2S		TOTAL			935	985	94.92
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.000s	3.006ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1542	1602	96.25

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	97.62	94.63	98.78	93.28	97.99	91.11	98.85	98.39

Failure Buckets

Job timed out after * minutes has 33 failures:
- Test aes_cipher_fi has 20 failures.
  - 2.aes_cipher_fi.26611121189739419354875251252296637244287560294008059372836317110978243721662
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 16.aes_cipher_fi.107237363020147529020184647741257555154159191157861655059799989664891463080010
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 18 more failures.
- Test aes_control_fi has 13 failures.
  - 21.aes_control_fi.83715547879091977760008711765901464025147449808913947423167714570969046467822
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 33.aes_control_fi.35154078773255963780170042090221015345310799567648412170636889354837115241275
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.96301638386442576540066481157467788342109661072676321684498688107999146203141
Line 257, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  52618824 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  52618824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.84150496466205784882077516157741119202773707891960040162384736454633168370158
Line 320, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 687984958 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 687984958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 10.aes_control_fi.38965970357039332431159657668004651645747595691092647241984991400757655021271
    Line 149, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013973733 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013973733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 188.aes_control_fi.63470640003997154476729026428980617952021078697282694913097921047912172861524
    Line 148, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/188.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008011764 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008011764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 55.aes_cipher_fi.2283064709389398524603930014264158897282554969895044768200866148404170010429
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/55.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005095683 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005095683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 231.aes_cipher_fi.96308478817206201012008830624479249830552423562785070896976712141628575275423
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/231.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010439943 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010439943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 45.aes_core_fi.80741766854277837245419400160749772877042883885719966635113841649739755998707
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/45.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025140309 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025140309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 46.aes_core_fi.45394851109763579217282423175485182394598113387212040947169339118406400217370
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/46.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10035403209 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035403209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.59780764392062257186355458630111541052839129601547583967069369119616724608164
    Line 1132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3791331050 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3791331050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.106769096550938212901539612220378523192516828383540114389968187455351159830834
    Line 389, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  90248419 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  90248419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 68.aes_core_fi.111282237963585715031581987120283577556997749856193550397368140783501630545081
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/68.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003808413 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003808413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```