CSRNG Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	170.843us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	29.275us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	56.218us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	42.000s	2.735ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	264.308us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	10.000s	442.967us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	56.218us	20	20	100.00
		csrng_csr_aliasing	7.000s	264.308us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	21.000s	831.996us	169	200	84.50
V2	alerts	csrng_alert	56.000s	4.603ms	500	500	100.00
V2	err	csrng_err	7.000s	103.391us	449	500	89.80
V2	cmds	csrng_cmds	20.633m	110.366ms	50	50	100.00
V2	life cycle	csrng_cmds	20.633m	110.366ms	50	50	100.00
V2	stress_all	csrng_stress_all	18.167m	57.391ms	48	50	96.00
V2	intr_test	csrng_intr_test	6.000s	100.024us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	54.162us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	997.591us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	997.591us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	29.275us	5	5	100.00
		csrng_csr_rw	6.000s	56.218us	20	20	100.00
		csrng_csr_aliasing	7.000s	264.308us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	200.614us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	29.275us	5	5	100.00
		csrng_csr_rw	6.000s	56.218us	20	20	100.00
		csrng_csr_aliasing	7.000s	264.308us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	200.614us	20	20	100.00
V2		TOTAL			1356	1440	94.17
V2S	tl_intg_err	csrng_sec_cm	19.000s	488.955us	5	5	100.00
		csrng_tl_intg_err	12.000s	573.867us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	126.526us	50	50	100.00
		csrng_csr_rw	6.000s	56.218us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	56.000s	4.603ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	18.167m	57.391ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
		csrng_sec_cm	19.000s	488.955us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
		csrng_sec_cm	19.000s	488.955us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
		csrng_sec_cm	19.000s	488.955us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
		csrng_sec_cm	19.000s	488.955us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
		csrng_sec_cm	19.000s	488.955us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
		csrng_sec_cm	19.000s	488.955us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
		csrng_sec_cm	19.000s	488.955us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	56.000s	4.603ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	18.167m	57.391ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	56.000s	4.603ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	573.867us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
		csrng_sec_cm	19.000s	488.955us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
		csrng_sec_cm	19.000s	488.955us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	21.000s	831.996us	169	200	84.50
		csrng_err	7.000s	103.391us	449	500	89.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	4.300m	23.596ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1536	1630	94.23

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.54	98.51	96.38	99.83	97.36	92.02	88.00	96.13	89.83

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_control_fsm.sv,452): Assertion u_state_regs_A has failed has 41 failures:
  • Test csrng_intr has 16 failures.

    • 11.csrng_intr.105760018477179222846483993130566911622933030812607672163786147260818666102230
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/11.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 414628822 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
        UVM_ERROR @ 414628822 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @ 414628822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 41.csrng_intr.47284061645616152815692061264086912841024177568993360420024306356941650659124
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/41.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 186693640 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[1].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
        UVM_ERROR @ 186693640 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @ 186693640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 14 more failures.

  • Test csrng_err has 25 failures.

    • 45.csrng_err.114532833836441788924623463731247355653129345423376991696342774496710471613914
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/45.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 2125321 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[1].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
        UVM_ERROR @   2125321 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @   2125321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 104.csrng_err.110638065421085092614947482962127348025417721919080362510492605167693443002105
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/104.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 3168363 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
        UVM_ERROR @   3168363 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @   3168363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 23 more failures.

• UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
  • Test csrng_stress_all_with_rand_reset has 10 failures.

    • 0.csrng_stress_all_with_rand_reset.22569615190966255765349488158238510585154520108696307998635049800969170048959
      Line 105, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1560167772 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1560167772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.csrng_stress_all_with_rand_reset.87604492254064277625666043621075738782099350679481213097656392661304356525889
      Line 110, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9184746660 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9184746660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,188): Assertion u_blk_enc_state_regs_A has failed has 10 failures:
  • Test csrng_err has 5 failures.

    • 3.csrng_err.98257027873871490683556444440985101650799431620689267684239788811854187056475
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/3.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 2458404 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
        UVM_ERROR @   2458404 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
        UVM_INFO @   2458404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 89.csrng_err.76223128705737103010374709530900206938058982319386839933144800092208045489927
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/89.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 4038424 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
        UVM_ERROR @   4038424 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
        UVM_INFO @   4038424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test csrng_intr has 5 failures.

    • 16.csrng_intr.98952742294999527063558533892014187447787971726598922934192417227916362924994
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/16.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 283476185 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
        UVM_ERROR @ 283476185 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
        UVM_INFO @ 283476185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 20.csrng_intr.16566580638787054252237164870129755777306924750195526497669611438730895518176
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/20.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 172638760 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
        UVM_ERROR @ 172638760 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
        UVM_INFO @ 172638760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_main_sm.sv,35): Assertion u_state_regs_A has failed has 10 failures:
  • Test csrng_err has 10 failures.

    • 49.csrng_err.86365840367824293278707251936402147739989932215222910549800050841370154560151
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/49.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 1685821 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
        UVM_ERROR @   1685821 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @   1685821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 91.csrng_err.63662408299148532253337349169356227788317596774981986483124924854661256016685
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/91.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 3623376 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
        UVM_ERROR @   3623376 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @   3623376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_gen.sv,222): Assertion u_state_regs_A has failed has 8 failures:

  • Test csrng_intr has 1 failures.

    • 108.csrng_intr.38282705010382795642595388015714106155843901713835224632994311341772331446711
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/108.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 67791871 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
        UVM_ERROR @  67791871 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  67791871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test csrng_err has 7 failures.

    • 125.csrng_err.44738076523455051429367442855659870240161812364021774128743488447462124292158
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/125.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 8399471 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
        UVM_ERROR @   8399471 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @   8399471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 138.csrng_err.79783563644888355273975673403334613764458910733794627968672959471899901038316
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/138.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 4276022 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
        UVM_ERROR @   4276022 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @   4276022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,222): Assertion u_outblk_state_regs_A has failed has 6 failures:

  • Test csrng_intr has 2 failures.

    • 67.csrng_intr.12344063593079775690267998043473160917498570659198014103258945826397401810566
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/67.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 39781954 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
        UVM_ERROR @  39781954 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
        UVM_INFO @  39781954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 182.csrng_intr.100917037628684770064527289960723310067742763021706667697338972927036596762707
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/182.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 291500808 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
        UVM_ERROR @ 291500808 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
        UVM_INFO @ 291500808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test csrng_err has 4 failures.

    • 133.csrng_err.87237864869956062936464088210755852709878475763180645151285023090372728456527
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/133.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 2358376 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
        UVM_ERROR @   2358376 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
        UVM_INFO @   2358376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 149.csrng_err.31807817945888055691330933595140289603570754267863353686938221352057846089085
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/149.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 2443905 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
        UVM_ERROR @   2443905 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
        UVM_INFO @   2443905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,260): Assertion u_state_regs_A has failed has 4 failures:
  • Test csrng_intr has 4 failures.

    • 36.csrng_intr.2334905935264030665839001035076604797124463627730750987915772069078394536205
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/36.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,260): (time 54726101 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.u_state_regs_A has failed
        UVM_ERROR @  54726101 ps: (csrng_cmd_stage.sv:260) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  54726101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 72.csrng_intr.111761815720195138999168619044154791512929551768712970516119957334895309548156
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/72.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,260): (time 85026553 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.u_state_regs_A has failed
        UVM_ERROR @  85026553 ps: (csrng_cmd_stage.sv:260) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  85026553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 3 failures:
  • Test csrng_intr has 3 failures.

    • 7.csrng_intr.104952554307593990639949415306116515586553769427391006817089892514350089174291
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/7.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 66813716 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
        UVM_ERROR @  66813716 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
        UVM_INFO @  66813716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 113.csrng_intr.74733722023374807907792740792805410384228287766542741047988724783091344790949
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/113.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 326039039 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
        UVM_ERROR @ 326039039 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
        UVM_INFO @ 326039039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
  • Test csrng_stress_all has 2 failures.

    • 17.csrng_stress_all.74921523823929111434364676735511887668803433333142443491895338254782827815226
      Line 160, in log /nightly/runs/scratch/master/csrng-sim-xcelium/17.csrng_stress_all/latest/run.log

        UVM_ERROR @ 14345184576 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 14345184576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 20.csrng_stress_all.17478149057553609503923888649386826071338405588378275768828480129545318379410
      Line 161, in log /nightly/runs/scratch/master/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log

        UVM_ERROR @ 5007297070 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 5007297070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---