DMA Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	12.000s	2.399ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	13.000s	868.455us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	12.000s	433.631us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	16.000s	104.052us	5	5	100.00
V1	csr_rw	dma_csr_rw	16.000s	26.159us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	22.000s	6.794ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	20.000s	2.009ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	6.000s	144.321us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	16.000s	26.159us	20	20	100.00
		dma_csr_aliasing	20.000s	2.009ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.483m	75.490ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	50.567m	963.721ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	46.767m	1.963s	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	38.483m	679.687ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	50.567m	963.721ms	3	3	100.00
V2	dma_abort	dma_abort	21.000s	5.563ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	4.783m	41.792ms	3	3	100.00
V2	intr_test	dma_intr_test	18.000s	12.261us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	40.000s	226.926us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	40.000s	226.926us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	16.000s	104.052us	5	5	100.00
		dma_csr_rw	16.000s	26.159us	20	20	100.00
		dma_csr_aliasing	20.000s	2.009ms	5	5	100.00
		dma_same_csr_outstanding	7.000s	105.051us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	16.000s	104.052us	5	5	100.00
		dma_csr_rw	16.000s	26.159us	20	20	100.00
		dma_csr_aliasing	20.000s	2.009ms	5	5	100.00
		dma_same_csr_outstanding	7.000s	105.051us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	46.000s	246.290us	5	5	100.00
		dma_generic_stress	38.483m	679.687ms	5	5	100.00
		dma_handshake_stress	50.567m	963.721ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	39.000s	689.176us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.683m	8.155ms	5	5	100.00
		dma_longer_transfer	11.000s	1.059ms	5	5	100.00
		TOTAL			304	304	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.65	96.97	95.19	96.28	95.97	77.31	82.76	97.77	42.72