EDN Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.620s 14.747us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.080s 26.645us 5 5 100.00
V1 csr_rw edn_csr_rw 2.500s 14.393us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.470s 666.077us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.390s 68.813us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 3.470s 114.681us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.500s 14.393us 20 20 100.00
edn_csr_aliasing 2.390s 68.813us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.900s 694.117us 300 300 100.00
V2 csrng_commands edn_genbits 5.900s 694.117us 300 300 100.00
V2 genbits edn_genbits 5.900s 694.117us 300 300 100.00
V2 interrupts edn_intr 2.770s 22.807us 50 50 100.00
V2 alerts edn_alert 3.110s 453.691us 200 200 100.00
V2 errs edn_err 2.880s 21.132us 100 100 100.00
V2 disable edn_disable 2.420s 11.192us 50 50 100.00
edn_disable_auto_req_mode 2.940s 130.717us 50 50 100.00
V2 stress_all edn_stress_all 8.140s 309.640us 50 50 100.00
V2 intr_test edn_intr_test 2.570s 19.866us 50 50 100.00
V2 alert_test edn_alert_test 2.760s 57.792us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.760s 519.802us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.760s 519.802us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.080s 26.645us 5 5 100.00
edn_csr_rw 2.500s 14.393us 20 20 100.00
edn_csr_aliasing 2.390s 68.813us 5 5 100.00
edn_same_csr_outstanding 2.870s 55.107us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.080s 26.645us 5 5 100.00
edn_csr_rw 2.500s 14.393us 20 20 100.00
edn_csr_aliasing 2.390s 68.813us 5 5 100.00
edn_same_csr_outstanding 2.870s 55.107us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.050s 540.754us 5 5 100.00
edn_tl_intg_err 11.050s 750.957us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.510s 26.811us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 3.110s 453.691us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.050s 540.754us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.050s 540.754us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.050s 540.754us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.050s 540.754us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 3.110s 453.691us 200 200 100.00
edn_sec_cm 9.050s 540.754us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 3.110s 453.691us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 11.050s 750.957us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.979m 15.206ms 28 50 56.00
V3 TOTAL 28 50 56.00
TOTAL 1108 1130 98.05

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.81 98.87 94.29 96.97 91.28 96.33 99.78 93.13

Failure Buckets