HMAC Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	12.460s	3.634ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.250s	38.155us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.340s	29.144us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.230s	313.014us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.110s	808.471us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	21.477m	587.496ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.340s	29.144us	20	20	100.00
		hmac_csr_aliasing	7.110s	808.471us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	2.291m	19.411ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.821m	2.070ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.360m	5.869ms	30	30	100.00
		hmac_test_sha384_vectors	8.950m	15.784ms	75	75	100.00
		hmac_test_sha512_vectors	9.033m	50.930ms	75	75	100.00
		hmac_test_hmac256_vectors	16.980s	1.421ms	50	50	100.00
		hmac_test_hmac384_vectors	17.730s	383.913us	60	60	100.00
		hmac_test_hmac512_vectors	19.190s	2.245ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	49.820s	5.435ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	25.115m	8.153ms	10	10	100.00
V2	error	hmac_error	2.485m	86.393ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	2.055m	11.641ms	10	10	100.00
V2	save_and_restore	hmac_smoke	12.460s	3.634ms	10	10	100.00
		hmac_long_msg	2.291m	19.411ms	10	10	100.00
		hmac_back_pressure	1.821m	2.070ms	25	25	100.00
		hmac_datapath_stress	25.115m	8.153ms	10	10	100.00
		hmac_burst_wr	49.820s	5.435ms	50	50	100.00
		hmac_stress_all	38.433m	348.121ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	12.460s	3.634ms	10	10	100.00
		hmac_long_msg	2.291m	19.411ms	10	10	100.00
		hmac_back_pressure	1.821m	2.070ms	25	25	100.00
		hmac_datapath_stress	25.115m	8.153ms	10	10	100.00
		hmac_wipe_secret	2.055m	11.641ms	10	10	100.00
		hmac_test_sha256_vectors	4.360m	5.869ms	30	30	100.00
		hmac_test_sha384_vectors	8.950m	15.784ms	75	75	100.00
		hmac_test_sha512_vectors	9.033m	50.930ms	75	75	100.00
		hmac_test_hmac256_vectors	16.980s	1.421ms	50	50	100.00
		hmac_test_hmac384_vectors	17.730s	383.913us	60	60	100.00
		hmac_test_hmac512_vectors	19.190s	2.245ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	12.460s	3.634ms	10	10	100.00
		hmac_long_msg	2.291m	19.411ms	10	10	100.00
		hmac_back_pressure	1.821m	2.070ms	25	25	100.00
		hmac_datapath_stress	25.115m	8.153ms	10	10	100.00
		hmac_burst_wr	49.820s	5.435ms	50	50	100.00
		hmac_error	2.485m	86.393ms	10	10	100.00
		hmac_wipe_secret	2.055m	11.641ms	10	10	100.00
		hmac_test_sha256_vectors	4.360m	5.869ms	30	30	100.00
		hmac_test_sha384_vectors	8.950m	15.784ms	75	75	100.00
		hmac_test_sha512_vectors	9.033m	50.930ms	75	75	100.00
		hmac_test_hmac256_vectors	16.980s	1.421ms	50	50	100.00
		hmac_test_hmac384_vectors	17.730s	383.913us	60	60	100.00
		hmac_test_hmac512_vectors	19.190s	2.245ms	75	75	100.00
		hmac_stress_all	38.433m	348.121ms	50	50	100.00
V2	stress_all	hmac_stress_all	38.433m	348.121ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.020s	45.193us	50	50	100.00
V2	intr_test	hmac_intr_test	2.150s	109.552us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.380s	357.163us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.380s	357.163us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.250s	38.155us	5	5	100.00
		hmac_csr_rw	2.340s	29.144us	20	20	100.00
		hmac_csr_aliasing	7.110s	808.471us	5	5	100.00
		hmac_same_csr_outstanding	4.080s	571.367us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.250s	38.155us	5	5	100.00
		hmac_csr_rw	2.340s	29.144us	20	20	100.00
		hmac_csr_aliasing	7.110s	808.471us	5	5	100.00
		hmac_same_csr_outstanding	4.080s	571.367us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.400s	204.592us	5	5	100.00
		hmac_tl_intg_err	6.020s	292.016us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.020s	292.016us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	12.460s	3.634ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	9.370s	531.569us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.412m	15.124ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.600s	111.201us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.96	99.84	97.20	100.00	100.00	99.83	99.52	47.30