I2C Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.269m	14.130ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	41.770s	1.246ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.400s	47.989us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.420s	35.663us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.170s	1.641ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.010s	168.655us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.930s	59.186us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.420s	35.663us	20	20	100.00
		i2c_csr_aliasing	3.010s	168.655us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	11.180s	322.587us	48	50	96.00
V2	host_stress_all	i2c_host_stress_all	42.476m	32.430ms	19	50	38.00
V2	host_maxperf	i2c_host_perf	46.447m	31.061ms	49	50	98.00
V2	host_override	i2c_host_override	2.260s	99.300us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.496m	5.376ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.147m	11.505ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.900s	133.107us	50	50	100.00
		i2c_host_fifo_fmt_empty	24.370s	1.973ms	50	50	100.00
		i2c_host_fifo_reset_rx	12.870s	223.706us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.135m	43.038ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	37.000s	1.875ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.650s	685.086us	19	50	38.00
V2	target_glitch	i2c_target_glitch	12.900s	7.647ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	42.764m	82.641ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	8.270s	2.645ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.183m	7.071ms	50	50	100.00
		i2c_target_intr_smoke	11.720s	5.132ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.660s	267.423us	50	50	100.00
		i2c_target_fifo_reset_tx	3.640s	1.083ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	17.040m	56.566ms	50	50	100.00
		i2c_target_stress_rd	1.183m	7.071ms	50	50	100.00
		i2c_target_intr_stress_wr	9.116m	32.542ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	10.540s	1.541ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	3.216m	4.755ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	10.340s	6.041ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	39.510s	10.003ms	29	50	58.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.540s	3.741ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.170s	169.048us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	46.447m	31.061ms	49	50	98.00
		i2c_host_perf_precise	14.632m	23.282ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	37.000s	1.875ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	24.530s	1.249ms	47	50	94.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.360s	2.174ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.330s	2.448ms	50	50	100.00
		i2c_target_nack_txstretch	3.230s	513.669us	30	50	60.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	27.270s	1.387ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.700s	518.998us	50	50	100.00
V2	alert_test	i2c_alert_test	2.250s	16.447us	50	50	100.00
V2	intr_test	i2c_intr_test	2.470s	46.252us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	4.230s	116.430us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	4.230s	116.430us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.400s	47.989us	5	5	100.00
		i2c_csr_rw	2.420s	35.663us	20	20	100.00
		i2c_csr_aliasing	3.010s	168.655us	5	5	100.00
		i2c_same_csr_outstanding	2.860s	50.322us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.400s	47.989us	5	5	100.00
		i2c_csr_rw	2.420s	35.663us	20	20	100.00
		i2c_csr_aliasing	3.010s	168.655us	5	5	100.00
		i2c_same_csr_outstanding	2.860s	50.322us	20	20	100.00
V2		TOTAL			1678	1792	93.64
V2S	tl_intg_err	i2c_tl_intg_err	4.280s	2.168ms	20	20	100.00
		i2c_sec_cm	2.560s	654.445us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	4.280s	2.168ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	25.310s	3.552ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	5.750s	6.473ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	54.550s	9.857ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1858	2042	90.99

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.02	97.47	89.70	74.17	72.02	94.18	98.52	90.06

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 34 failures:

Test i2c_host_mode_toggle has 14 failures.

0.i2c_host_mode_toggle.21116441254154874750383655512770151109130744701002451499228897620433437774013
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 147656995 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @25601

4.i2c_host_mode_toggle.39461922456539262918840819254030073537871910106898141645423596712425668444194
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 117198829 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @18981

... and 12 more failures.

Test i2c_host_stress_all has 20 failures.

5.i2c_host_stress_all.95620783034588507515557292081221979597840833086078203929226294136664826986505
Line 232, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 41490158245 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1252452

8.i2c_host_stress_all.27892682526114962625794056704373553281976577595635349171875145719676066007196
Line 114, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 18350615838 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2267938

... and 18 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 28 failures:
- Test i2c_target_unexp_stop has 27 failures.
  - 0.i2c_target_unexp_stop.53528551267803245543380966625628753050538319315574184721688633219394397217998
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  20132137 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 71 [0x47])
  UVM_INFO @  20132137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.66216048240765184730651502281185630360694847183442424065176241460215747425972
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 122709165 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 8 [0x8])
  UVM_INFO @ 122709165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 25 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 6.i2c_target_stress_all_with_rand_reset.70396577042599356469664053834322719754099810745002644282353150853782439767977
    Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  60473049 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 93 [0x5d])
  UVM_INFO @  60473049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 21 failures:
- Test i2c_target_hrst has 21 failures.
  - 1.i2c_target_hrst.33410721692515537092934447999500937630034371559082614087200606843803329761825
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10226895968 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10226895968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.i2c_target_hrst.92920803078866188214227664734072463407605405885526891242550634172647189991143
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10003121322 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10003121322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 20 failures:
- Test i2c_target_nack_txstretch has 20 failures.
  - 3.i2c_target_nack_txstretch.47644911081890569127469190261025090294907545581426949988307907220916407859091
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 764900256 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 764900256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_nack_txstretch.110686718012866611029418966192328941162628776523939636789889467502030231792451
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 132041725 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 132041725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.76305106584064843481155153342803984045208435098959867135771297139154894751117
Line 94, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 757108672 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 757108672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.6171510538094716714527863803220176977577420572152035326797579448851781990031
Line 101, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2382058132 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2382058132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 9 failures.

0.i2c_target_stress_all_with_rand_reset.80781396696523613524946062575521497431555983437360200084203049261649990836344
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2883344343 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2883344343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.107360065068675152084302479640685613881293463676684254076604586838589070003855
Line 100, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 896016396 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 896016396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
- Test i2c_target_unexp_stop has 17 failures.
  - 8.i2c_target_unexp_stop.49082412846051296018306390817031336968248239575557636736676058526464024739594
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 418840472 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 418840472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.i2c_target_unexp_stop.102598948762100076290375672981561291527897079484683401913962220072289368232042
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1070599167 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1070599167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 15 failures:

Test i2c_host_mode_toggle has 15 failures.

1.i2c_host_mode_toggle.101496368081297080889807973705672242949746500574385561244630764780158458672498
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  75304512 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

2.i2c_host_mode_toggle.44472046483421674399077184340026367532705716993734107379935563922944954400738
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  86551327 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 13 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:

Test i2c_target_unexp_stop has 6 failures.

2.i2c_target_unexp_stop.102655630971453324442507405898988067412922884774659924069236695732127573594640
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 531054376 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 531054376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_unexp_stop.65305763017378844843520516315070904172543147583819208192665298349149630387041
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 368554273 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 368554273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Job timed out after * minutes has 5 failures:
- Test i2c_host_error_intr has 1 failures.
  - 6.i2c_host_error_intr.59539334366383686565766046044609143125637675900110471881232699920300476447904
    Log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_host_error_intr/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_stress_all has 4 failures.
  - 24.i2c_host_stress_all.63146832179795140287189506759913318402012047484934275743042990975226098490647
    Log /nightly/runs/scratch/master/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 30.i2c_host_stress_all.19884720535775866760228745202230102561945246894105515043876405838527852535216
    Log /nightly/runs/scratch/master/i2c-sim-vcs/30.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
- Test i2c_target_stretch has 4 failures.
  - 1.i2c_target_stretch.69703364291251573775027411899645604116545333568304258560769688204840106412195
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10050911378 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10050911378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 20.i2c_target_stretch.53855286304743932923679858780298065088158825012375026818422018982537446911725
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/20.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10049091397 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10049091397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:

Test i2c_host_stress_all has 4 failures.

6.i2c_host_stress_all.67087959466266485940707100343777938559054768017090723834267644546311663175467
Line 202, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 18792825307 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4300194

23.i2c_host_stress_all.63323289010728762984420428048008731401889647158569500705183291247378203545882
Line 289, in log /nightly/runs/scratch/master/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 53442110344 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @6573150

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test i2c_host_stress_all has 3 failures.
  - 16.i2c_host_stress_all.45929321570455273455279830535259275830842120638532459578174545480618471426218
    Line 103, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 18.i2c_host_stress_all.101921303492622248028074904377662681527901202520648597038915875211064244946523
    Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test i2c_host_perf has 1 failures.
  - 39.i2c_host_perf.53856540086480850407471274463268564379240616907030702264942347498059977521654
    Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/39.i2c_host_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test i2c_target_tx_stretch_ctrl has 3 failures.
  - 7.i2c_target_tx_stretch_ctrl.1161350469087609541276883308542797411536062584825199914382983961544118297266
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 9.i2c_target_tx_stretch_ctrl.95701890362295765113158329304678870239593716702418190524789892159297694820970
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:

Test i2c_host_mode_toggle has 2 failures.

37.i2c_host_mode_toggle.78892021251840934926083569328270145427416119860477407573650889719369927087027
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/37.i2c_host_mode_toggle/latest/run.log

  UVM_FATAL @ 121067913 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xaaf53094, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 121067913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.i2c_host_mode_toggle.81951840289939985892848840367867074970989581867027266783234542133676356770786
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/41.i2c_host_mode_toggle/latest/run.log

  UVM_FATAL @ 105564713 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x98b4ff14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 105564713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
- Test i2c_target_intr_stress_wr has 1 failures.
  - 6.i2c_target_intr_stress_wr.91170106293119129568817642290421345739867136390314637872471526526093575541979
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 50798553099 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 50798553099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_error_intr has 1 failures.
  - 48.i2c_host_error_intr.33773502637458124823236881546188975504778128376252470922049275344446790397760
    Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/48.i2c_host_error_intr/latest/run.log
```
  UVM_ERROR @  43278704 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```