KEYMGR Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	33.680s	5.539ms	50	50	100.00
V1	random	keymgr_random	41.470s	5.699ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	3.020s	47.350us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.530s	87.734us	17	20	85.00
V1	csr_bit_bash	keymgr_csr_bit_bash	12.410s	3.287ms	3	5	60.00
V1	csr_aliasing	keymgr_csr_aliasing	8.860s	767.117us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.570s	31.288us	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.530s	87.734us	17	20	85.00
		keymgr_csr_aliasing	8.860s	767.117us	4	5	80.00
V1		TOTAL			145	155	93.55
V2	cfgen_during_op	keymgr_cfg_regwen	1.541m	8.551ms	50	50	100.00
V2	sideload	keymgr_sideload	45.270s	5.817ms	50	50	100.00
		keymgr_sideload_kmac	41.890s	1.768ms	50	50	100.00
		keymgr_sideload_aes	30.170s	2.707ms	50	50	100.00
		keymgr_sideload_otbn	30.860s	1.691ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	16.470s	653.700us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	18.630s	693.441us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	10.000s	412.219us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.021m	6.889ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.059m	3.314ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	18.740s	2.670ms	50	50	100.00
V2	stress_all	keymgr_stress_all	2.613m	34.599ms	49	50	98.00
V2	intr_test	keymgr_intr_test	2.260s	12.045us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.550s	21.641us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.180s	128.376us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.180s	128.376us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	3.020s	47.350us	5	5	100.00
		keymgr_csr_rw	2.530s	87.734us	17	20	85.00
		keymgr_csr_aliasing	8.860s	767.117us	4	5	80.00
		keymgr_same_csr_outstanding	4.270s	96.073us	15	20	75.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	3.020s	47.350us	5	5	100.00
		keymgr_csr_rw	2.530s	87.734us	17	20	85.00
		keymgr_csr_aliasing	8.860s	767.117us	4	5	80.00
		keymgr_same_csr_outstanding	4.270s	96.073us	15	20	75.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
		keymgr_tl_intg_err	7.020s	967.381us	10	20	50.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.790s	984.127us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.790s	984.127us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.790s	984.127us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.790s	984.127us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.980s	790.649us	14	20	70.00
V2S	prim_count_check	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.020s	967.381us	10	20	50.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.790s	984.127us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.541m	8.551ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	41.470s	5.699ms	50	50	100.00
		keymgr_csr_rw	2.530s	87.734us	17	20	85.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	41.470s	5.699ms	50	50	100.00
		keymgr_csr_rw	2.530s	87.734us	17	20	85.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	41.470s	5.699ms	50	50	100.00
		keymgr_csr_rw	2.530s	87.734us	17	20	85.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	18.630s	693.441us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.059m	3.314ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.059m	3.314ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	41.470s	5.699ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	21.460s	7.939ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	7.370s	330.349us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	18.630s	693.441us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	7.370s	330.349us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	7.370s	330.349us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	7.370s	330.349us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.230s	4.901ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	7.370s	330.349us	50	50	100.00
V2S		TOTAL			149	165	90.30
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.070s	2.192ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1058	1110	95.32

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.82	99.13	98.15	98.56	100.00	99.01	98.63	91.23

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 31 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 6 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.72944002942057295663746632851450500200837507184578225226719533491133249867497
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @  28577273 ps: (keymgr_csr_assert_fpv.sv:430) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @  28577273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_shadow_reg_errors_with_csr_rw.12435937653449942982649584687527038824490853613552546111019680752544448855219
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @ 251141409 ps: (keymgr_csr_assert_fpv.sv:418) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @ 251141409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_tl_intg_err has 10 failures.

0.keymgr_tl_intg_err.79670737564175108336174127264825295658905713846376831530130059865849997364755
Line 90, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @  24112620 ps: (keymgr_csr_assert_fpv.sv:430) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @  24112620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_tl_intg_err.2818407188778716441071402276154653001534151079695400087149110371712439800675
Line 100, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @ 332761220 ps: (keymgr_csr_assert_fpv.sv:472) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @ 332761220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test keymgr_csr_rw has 3 failures.

0.keymgr_csr_rw.65652670367215361651091523524685669979006184025053119158765036092985061910867
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @  50071788 ps: (keymgr_csr_assert_fpv.sv:430) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @  50071788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.keymgr_csr_rw.101930839164725429367588190928991051137770042533671205050181953809028328289948
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/14.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @  12563828 ps: (keymgr_csr_assert_fpv.sv:454) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @  12563828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_same_csr_outstanding has 5 failures.

1.keymgr_same_csr_outstanding.71027526531073079957633441919496468997210730671535782710194446435174254048552
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @ 170357470 ps: (keymgr_csr_assert_fpv.sv:460) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @ 170357470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_same_csr_outstanding.86666513932994912523617386949899609005500526098608869176841463362223372127884
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @  61769203 ps: (keymgr_csr_assert_fpv.sv:424) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @  61769203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_bit_bash has 2 failures.

2.keymgr_csr_bit_bash.59115632296652586912379299692652847170426299885309325612628357672602080606406
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @ 390165359 ps: (keymgr_csr_assert_fpv.sv:448) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @ 390165359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_csr_bit_bash.85492025316947423707139618258684523764047573760787632429387218935888831041616
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @ 2611511190 ps: (keymgr_csr_assert_fpv.sv:454) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @ 2611511190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test keymgr_stress_all_with_rand_reset has 17 failures.
  - 2.keymgr_stress_all_with_rand_reset.49840151006929153199098578263456478355127026788751398646076516218245018975776
    Line 536, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 988281749 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 988281749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.69826755240083289376726514416789191718380204832133955271642632565815265508428
    Line 1123, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1397258021 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1397258021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 2 failures:
- Test keymgr_stress_all_with_rand_reset has 2 failures.
  - 36.keymgr_stress_all_with_rand_reset.3372410560962523693463815361512792211440753428814295416061435940727669075562
    Line 241, in log /nightly/runs/scratch/master/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 524933102 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 524933102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 49.keymgr_stress_all_with_rand_reset.16468766909729575088346142210154415051600804131143805109028653231765940357800
    Line 438, in log /nightly/runs/scratch/master/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 220835385 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 220835385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 2.keymgr_lc_disable.92261762772789607311886470749199180764554855316787126853079977658879834932432
    Line 189, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  13139110 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  13139110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 5.keymgr_stress_all.114253610890223120057703389222123451919785903558149470502835229520577455787779
    Line 2261, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 3500219218 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_7
  UVM_INFO @ 3500219218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```