KEYMGR_DPE Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	2.630m	41.028ms	50	50	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	2.210s	88.960us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	2.630s	17.599us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	17.180s	14.115ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	8.090s	298.739us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	3.530s	87.290us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	2.630s	17.599us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.090s	298.739us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	intr_test	keymgr_dpe_intr_test	2.600s	14.294us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	2.570s	15.418us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	4.410s	1.757ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	4.410s	1.757ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	2.210s	88.960us	5	5	100.00
		keymgr_dpe_csr_rw	2.630s	17.599us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.090s	298.739us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.450s	99.231us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	2.210s	88.960us	5	5	100.00
		keymgr_dpe_csr_rw	2.630s	17.599us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.090s	298.739us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.450s	99.231us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	18.960s	941.784us	5	5	100.00
		keymgr_dpe_tl_intg_err	8.770s	364.775us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	4.360s	375.104us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	4.360s	375.104us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	4.360s	375.104us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	4.360s	375.104us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	7.640s	1.224ms	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	18.960s	941.784us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	18.960s	941.784us	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			310	310	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.07	97.63	90.57	63.14	76.92	94.89	98.57	17.75