KMAC/MASKED Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.659m	8.356ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.630s	220.391us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.650s	162.340us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.930s	1.002ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.770s	2.276ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.890s	171.321us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.650s	162.340us	20	20	100.00
		kmac_csr_aliasing	9.770s	2.276ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.190s	12.931us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.940s	38.480us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	54.372m	721.323ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.961m	46.864ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	25.657m	18.366ms	5	5	100.00
		kmac_test_vectors_sha3_256	37.077m	158.511ms	5	5	100.00
		kmac_test_vectors_sha3_384	22.470m	43.907ms	5	5	100.00
		kmac_test_vectors_sha3_512	20.282m	32.715ms	5	5	100.00
		kmac_test_vectors_shake_128	46.987m	205.562ms	5	5	100.00
		kmac_test_vectors_shake_256	6.110m	34.543ms	5	5	100.00
		kmac_test_vectors_kmac	5.170s	113.005us	5	5	100.00
		kmac_test_vectors_kmac_xof	5.170s	462.471us	5	5	100.00
V2	sideload	kmac_sideload	8.934m	47.712ms	50	50	100.00
V2	app	kmac_app	6.801m	26.040ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.205m	20.616ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.621m	18.787ms	50	50	100.00
V2	error	kmac_error	8.608m	125.577ms	50	50	100.00
V2	key_error	kmac_key_error	19.620s	1.911ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.050s	296.518us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	53.140s	1.593ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	16.860s	619.643us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.501m	7.027ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.130s	2.709ms	50	50	100.00
V2	stress_all	kmac_stress_all	51.436m	533.767ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.310s	51.597us	50	50	100.00
V2	alert_test	kmac_alert_test	2.410s	21.612us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.270s	152.908us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.270s	152.908us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.630s	220.391us	5	5	100.00
		kmac_csr_rw	2.650s	162.340us	20	20	100.00
		kmac_csr_aliasing	9.770s	2.276ms	5	5	100.00
		kmac_same_csr_outstanding	3.610s	88.648us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.630s	220.391us	5	5	100.00
		kmac_csr_rw	2.650s	162.340us	20	20	100.00
		kmac_csr_aliasing	9.770s	2.276ms	5	5	100.00
		kmac_same_csr_outstanding	3.610s	88.648us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.260s	92.751us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.260s	92.751us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.260s	92.751us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.260s	92.751us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.540s	1.113ms	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	2.330m	33.444ms	5	5	100.00
		kmac_tl_intg_err	5.740s	706.973us	11	20	55.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.740s	706.973us	11	20	55.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.130s	2.709ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.659m	8.356ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.934m	47.712ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.260s	92.751us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.330m	33.444ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.330m	33.444ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.330m	33.444ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.659m	8.356ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.130s	2.709ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.330m	33.444ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.714m	25.337ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.659m	8.356ms	50	50	100.00
V2S		TOTAL			59	75	78.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.909m	31.813ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			917	940	97.55

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.44	99.14	94.47	99.89	80.28	97.09	99.38	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 16 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

1.kmac_shadow_reg_errors_with_csr_rw.32005878851306386207933677651531757681486553000707406359313468649536951758992
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  23047579 ps: (kmac_csr_assert_fpv.sv:530) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  23047579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors_with_csr_rw.60585991802260001678521949609115427679712751199164584006413914450332119366431
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
  UVM_ERROR @  24631583 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_7_rd_A
  UVM_INFO @  24631583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_tl_intg_err has 9 failures.

1.kmac_tl_intg_err.32225296033453434673546915192452875700636272629168521030753385875170267865815
Line 86, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  22241984 ps: (kmac_csr_assert_fpv.sv:530) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  22241984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_tl_intg_err.103893403719295102637380951084947991911013483763495584480888158016355808120047
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  90934000 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  90934000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 2.kmac_stress_all_with_rand_reset.112945787111429896441309986050951114143702328404709254174898865237124553964552
    Line 163, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9383339638 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9383339638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.kmac_stress_all_with_rand_reset.65074058930888958938120717801482021857009610908841356031800310799620109078259
    Line 163, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14808578803 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 14808578803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 9.kmac_stress_all_with_rand_reset.28720480819871257013504861267381962142273405201172002165883879736315511366459
    Line 187, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13309462973 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13309462973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 13.kmac_burst_write.113389591356035591286700280779144394589771263258971379841975707213506634549427
    Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/13.kmac_burst_write/latest/run.log
```
  UVM_ERROR @  57707778 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  57707778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```