KMAC/UNMASKED Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.033m 4.120ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 2.890s 21.848us 5 5 100.00
V1 csr_rw kmac_csr_rw 2.850s 66.377us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 15.560s 2.819ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 9.220s 3.424ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 3.550s 94.578us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 2.850s 66.377us 20 20 100.00
kmac_csr_aliasing 9.220s 3.424ms 5 5 100.00
V1 mem_walk kmac_mem_walk 2.580s 22.134us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 3.340s 41.836us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 44.880m 174.345ms 50 50 100.00
V2 burst_write kmac_burst_write 15.076m 34.061ms 50 50 100.00
V2 test_vectors kmac_test_vectors_sha3_224 30.785m 374.235ms 5 5 100.00
kmac_test_vectors_sha3_256 25.920m 59.357ms 5 5 100.00
kmac_test_vectors_sha3_384 19.055m 358.365ms 5 5 100.00
kmac_test_vectors_sha3_512 9.154m 18.390ms 5 5 100.00
kmac_test_vectors_shake_128 36.402m 97.876ms 5 5 100.00
kmac_test_vectors_shake_256 20.084m 66.360ms 5 5 100.00
kmac_test_vectors_kmac 3.550s 116.268us 5 5 100.00
kmac_test_vectors_kmac_xof 3.620s 95.676us 5 5 100.00
V2 sideload kmac_sideload 6.676m 321.416ms 50 50 100.00
V2 app kmac_app 5.028m 27.512ms 50 50 100.00
V2 app_with_partial_data kmac_app_with_partial_data 4.929m 63.346ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 4.565m 91.103ms 50 50 100.00
V2 error kmac_error 6.723m 83.804ms 50 50 100.00
V2 key_error kmac_key_error 20.060s 19.873ms 50 50 100.00
V2 sideload_invalid kmac_sideload_invalid 2.095m 10.039ms 37 50 74.00
V2 edn_timeout_error kmac_edn_timeout_error 38.360s 6.540ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 35.130s 7.094ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 52.470s 9.120ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 35.710s 3.201ms 50 50 100.00
V2 stress_all kmac_stress_all 34.673m 113.631ms 50 50 100.00
V2 intr_test kmac_intr_test 2.610s 13.352us 50 50 100.00
V2 alert_test kmac_alert_test 2.270s 20.998us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 4.460s 165.326us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 4.460s 165.326us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 2.890s 21.848us 5 5 100.00
kmac_csr_rw 2.850s 66.377us 20 20 100.00
kmac_csr_aliasing 9.220s 3.424ms 5 5 100.00
kmac_same_csr_outstanding 3.880s 205.666us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 2.890s 21.848us 5 5 100.00
kmac_csr_rw 2.850s 66.377us 20 20 100.00
kmac_csr_aliasing 9.220s 3.424ms 5 5 100.00
kmac_same_csr_outstanding 3.880s 205.666us 20 20 100.00
V2 TOTAL 727 740 98.24
V2S shadow_reg_update_error kmac_shadow_reg_errors 3.160s 99.674us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 3.160s 99.674us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 3.160s 99.674us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 3.160s 99.674us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 4.900s 329.437us 12 20 60.00
V2S tl_intg_err kmac_sec_cm 1.070m 6.486ms 5 5 100.00
kmac_tl_intg_err 4.710s 369.929us 13 20 65.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 4.710s 369.929us 13 20 65.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 35.710s 3.201ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.033m 4.120ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 6.676m 321.416ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 3.160s 99.674us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.070m 6.486ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.070m 6.486ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.070m 6.486ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.033m 4.120ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 35.710s 3.201ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.070m 6.486ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 4.713m 75.309ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.033m 4.120ms 50 50 100.00
V2S TOTAL 60 75 80.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 3.617m 18.582ms 5 10 50.00
V3 TOTAL 5 10 50.00
TOTAL 907 940 96.49

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.00 97.23 94.42 100.00 75.21 95.98 99.35 95.84

Failure Buckets