OTBN Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	72.819us	1	1	100.00
V1	single_binary	otbn_single	33.000s	91.791us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	29.000s	30.236us	5	5	100.00
V1	csr_rw	otbn_csr_rw	27.000s	26.949us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	573.532us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	83.890us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	141.222us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	27.000s	26.949us	20	20	100.00
		otbn_csr_aliasing	7.000s	83.890us	5	5	100.00
V1	mem_walk	otbn_mem_walk	53.000s	2.498ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	43.000s	776.267us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.767m	468.139us	10	10	100.00
V2	multi_error	otbn_multi_err	1.400m	273.174us	1	1	100.00
V2	back_to_back	otbn_multi	1.300m	847.213us	10	10	100.00
V2	stress_all	otbn_stress_all	2.683m	564.981us	10	10	100.00
V2	lc_escalation	otbn_escalate	23.000s	49.939us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	39.955us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	105.258us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	31.697us	50	50	100.00
V2	intr_test	otbn_intr_test	38.000s	30.651us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	44.000s	113.405us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	44.000s	113.405us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	29.000s	30.236us	5	5	100.00
		otbn_csr_rw	27.000s	26.949us	20	20	100.00
		otbn_csr_aliasing	7.000s	83.890us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	31.709us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	29.000s	30.236us	5	5	100.00
		otbn_csr_rw	27.000s	26.949us	20	20	100.00
		otbn_csr_aliasing	7.000s	83.890us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	31.709us	20	20	100.00
V2		TOTAL			246	246	100.00
V2S	mem_integrity	otbn_imem_err	14.000s	30.573us	10	10	100.00
		otbn_dmem_err	22.000s	73.805us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	220.710us	5	5	100.00
		otbn_controller_ispr_rdata_err	22.000s	266.889us	5	5	100.00
		otbn_mac_bignum_acc_err	24.000s	83.322us	5	5	100.00
		otbn_urnd_err	11.000s	22.696us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	25.547us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	81.022us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	29.530us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
		otbn_tl_intg_err	50.000s	67.530us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	56.000s	91.772us	17	20	85.00
V2S	prim_fsm_check	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	72.819us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	22.000s	73.805us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	30.573us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	50.000s	67.530us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	23.000s	49.939us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	30.573us	10	10	100.00
		otbn_dmem_err	22.000s	73.805us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	39.955us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	25.547us	5	5	100.00
		otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	33.000s	91.791us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	30.573us	10	10	100.00
		otbn_dmem_err	22.000s	73.805us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	39.955us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	25.547us	5	5	100.00
		otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	23.000s	49.939us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	30.573us	10	10	100.00
		otbn_dmem_err	22.000s	73.805us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	39.955us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	25.547us	5	5	100.00
		otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	33.000s	91.791us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	24.646us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	23.608us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	43.000s	350.366us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	43.000s	350.366us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	68.775us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	135.803us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	40.810us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	40.810us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	17.261us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	33.000s	91.791us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	33.000s	91.791us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	33.000s	91.791us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.300m	847.213us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	33.000s	91.791us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	33.000s	91.791us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	22.000s	322.405us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	33.000s	91.791us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.117m	1.092ms	3	5	60.00
V2S		TOTAL			154	163	94.48
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.933m	2.352ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			570	585	97.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.10	99.64	96.00	99.73	93.22	93.43	100.00	98.19	100.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:

  • Test otbn_stress_all_with_rand_reset has 4 failures.

    • 0.otbn_stress_all_with_rand_reset.23382695526541509237736150803068219995083136297397870540867081007212534622313
      Line 263, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 972150327 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 972150327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.otbn_stress_all_with_rand_reset.103799875583954362415410510179805011476863435450149882537423850888336912023681
      Line 208, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 513891299 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 513891299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

  • Test otbn_sec_wipe_err has 3 failures.

    • 0.otbn_sec_wipe_err.17363614360288051055292056388931059769499407660288037721155200278292657138247
      Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17261177 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  17261177 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  17261177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.otbn_sec_wipe_err.32180459305831522964804781849087636812587648003366903286273497015583626906955
      Line 112, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 41183306 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  41183306 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  41183306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:

  • Test otbn_sec_cm has 2 failures.

    • 0.otbn_sec_cm.28244252124684659965305007919739265566189136219220717635535696880591012532353
      Line 99, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 414276814 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 414276814 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @ 414276814 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @ 414276814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.otbn_sec_cm.59098814509757380693015971941507236289849991459828699189964346918068031683761
      Line 108, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 142753110 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 142753110 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @ 142753110 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @ 142753110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:

  • Test otbn_stress_all_with_rand_reset has 2 failures.

    • 4.otbn_stress_all_with_rand_reset.32268449355880706340629137438030796120666527232545090119640245343403478223169
      Line 257, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 2249646569 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 2249646569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.otbn_stress_all_with_rand_reset.90318004639764618167738778245986053909393099284593619631755497460260571999447
      Line 164, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 534727651 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 534727651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:

  • Test otbn_passthru_mem_tl_intg_err has 2 failures.

    • 5.otbn_passthru_mem_tl_intg_err.107013466713747344849665252259603549476343549120678412286365583388492170698615
      Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @  39952638 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @  39952638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.otbn_passthru_mem_tl_intg_err.98801040789027960193427313518376152634118961818980477069671973063529356154105
      Line 127, in log /nightly/runs/scratch/master/otbn-sim-xcelium/11.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @  83642402 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @  83642402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed has 1 failures:

  • Test otbn_partial_wipe has 1 failures.

    • 9.otbn_partial_wipe.96890097738563415171366948131880620986629261892869698184498516028784273966475
      Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/9.otbn_partial_wipe/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 7932580 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
        UVM_ERROR @   7932580 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
        UVM_INFO @   7932580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:

  • Test otbn_passthru_mem_tl_intg_err has 1 failures.

    • 18.otbn_passthru_mem_tl_intg_err.40102987224474225865138076408070972850522402405489215370799485489386735162548
      Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/18.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @   1236560 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
        UVM_INFO @   1236560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---