ROM_CTRL/32KB Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.610s	511.458us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.070s	146.867us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.340s	164.029us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.980s	129.468us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.580s	167.269us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.820s	639.944us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.340s	164.029us	20	20	100.00
		rom_ctrl_csr_aliasing	7.580s	167.269us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.110s	1.918ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.070s	695.489us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.870s	315.012us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	38.360s	2.112ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	10.210s	303.107us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.530s	169.582us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.880s	615.852us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.880s	615.852us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.070s	146.867us	5	5	100.00
		rom_ctrl_csr_rw	7.340s	164.029us	20	20	100.00
		rom_ctrl_csr_aliasing	7.580s	167.269us	5	5	100.00
		rom_ctrl_same_csr_outstanding	11.250s	1.072ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.070s	146.867us	5	5	100.00
		rom_ctrl_csr_rw	7.340s	164.029us	20	20	100.00
		rom_ctrl_csr_aliasing	7.580s	167.269us	5	5	100.00
		rom_ctrl_same_csr_outstanding	11.250s	1.072ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.697m	6.068ms	15	20	75.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	32.580s	1.677ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.912m	1.977ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.096m	321.331us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.912m	1.977ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.912m	1.977ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.697m	6.068ms	15	20	75.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.697m	6.068ms	15	20	75.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.697m	6.068ms	15	20	75.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.697m	6.068ms	15	20	75.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.697m	6.068ms	15	20	75.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.912m	1.977ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.912m	1.977ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.610s	511.458us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.610s	511.458us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.610s	511.458us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.096m	321.331us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.697m	6.068ms	15	20	75.00
		rom_ctrl_kmac_err_chk	10.210s	303.107us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.697m	6.068ms	15	20	75.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.697m	6.068ms	15	20	75.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.697m	6.068ms	15	20	75.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	32.580s	1.677ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.912m	1.977ms	5	5	100.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	10.014m	22.746ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.40	99.59	98.68	100.00	100.00	99.28	98.98	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 5 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 5 failures.

    • 2.rom_ctrl_corrupt_sig_fatal_chk.107876528434663271145376411334126942510200531188931666989207781729200236321886
      Line 84, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1178324806 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1178324806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.rom_ctrl_corrupt_sig_fatal_chk.10061386945611506173640498691784043665422377049329355687685313541408564036058
      Line 86, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 477191164 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 477191164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.