RV_TIMER Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.160s	39.952us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.950s	24.645us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.120s	19.008us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.490s	1.064ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.060s	19.808us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.500s	108.044us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.120s	19.008us	20	20	100.00
		rv_timer_csr_aliasing	2.060s	19.808us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	17.050s	60.391ms	20	20	100.00
V2	disabled	rv_timer_disabled	3.770s	1.898ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	14.217m	2.931s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	14.217m	2.931s	10	10	100.00
V2	stress	rv_timer_stress_all	7.570s	10.771ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.230s	13.968us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.050s	11.619us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.710s	867.917us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.710s	867.917us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.950s	24.645us	5	5	100.00
		rv_timer_csr_rw	2.120s	19.008us	20	20	100.00
		rv_timer_csr_aliasing	2.060s	19.808us	5	5	100.00
		rv_timer_same_csr_outstanding	2.260s	16.507us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.950s	24.645us	5	5	100.00
		rv_timer_csr_rw	2.120s	19.008us	20	20	100.00
		rv_timer_csr_aliasing	2.060s	19.808us	5	5	100.00
		rv_timer_same_csr_outstanding	2.260s	16.507us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.440s	72.344us	5	5	100.00
		rv_timer_tl_intg_err	3.170s	116.264us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.170s	116.264us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	2.160s	35.121us	10	10	100.00
V3	max_value	rv_timer_max	2.070s	14.119us	10	10	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	58.820s	27.236ms	20	20	100.00
V3		TOTAL			40	40	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.44	100.00	100.00	78.66	--	100.00	100.00	100.00