SPI_DEVICE/1R1W Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.426m	597.118ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.680s	625.326us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.020s	571.911us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.490s	2.365ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.910s	1.893ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.050s	742.521us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.020s	571.911us	20	20	100.00
		spi_device_csr_aliasing	20.910s	1.893ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.190s	27.403us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.770s	111.422us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.450s	81.019us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.340s	3.031us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.880s	5.437us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.530s	163.371us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.530s	163.371us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	28.780s	6.293ms	50	50	100.00
		spi_device_tpm_sts_read	2.960s	194.338us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.920s	14.410ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.710s	20.318ms	50	50	100.00
		spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	43.370s	53.896ms	50	50	100.00
		spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	43.370s	53.896ms	50	50	100.00
		spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	25.950s	3.648ms	50	50	100.00
		spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	25.950s	3.648ms	50	50	100.00
		spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	25.950s	3.648ms	50	50	100.00
		spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	25.950s	3.648ms	50	50	100.00
		spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	25.950s	3.648ms	50	50	100.00
		spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	52.970s	51.903ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.126m	66.615ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.126m	66.615ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.126m	66.615ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	50.600s	18.092ms	50	50	100.00
		spi_device_read_buffer_direct	17.130s	2.161ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.126m	66.615ms	50	50	100.00
		spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.360m	79.676ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	14.180s	8.213ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	14.180s	8.213ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.426m	597.118ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.225m	57.109ms	50	50	100.00
V2	stress_all	spi_device_stress_all	8.701m	169.807ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.390s	42.867us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.400s	17.291us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.750s	947.732us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.750s	947.732us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.680s	625.326us	5	5	100.00
		spi_device_csr_rw	4.020s	571.911us	20	20	100.00
		spi_device_csr_aliasing	20.910s	1.893ms	5	5	100.00
		spi_device_same_csr_outstanding	5.100s	63.305us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.680s	625.326us	5	5	100.00
		spi_device_csr_rw	4.020s	571.911us	20	20	100.00
		spi_device_csr_aliasing	20.910s	1.893ms	5	5	100.00
		spi_device_same_csr_outstanding	5.100s	63.305us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.830s	82.811us	5	5	100.00
		spi_device_tl_intg_err	20.300s	824.336us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.300s	824.336us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.583m	59.303ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.80	99.11	96.52	71.19	89.36	98.39	95.76	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.108453758396218559202300153940641580604431666189620051951794426750663676227296
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3105260 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[98])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3105260 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3105260 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[994])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.101986880682223831132907274250381849635185220237972492095197987836671118814753
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    847045 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[40])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    847045 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    847045 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[936])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.112986271094272267492067582479137316496139235570821951226808739415174568367951
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3215196 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe9dde5 [111010011101110111100101] vs 0x0 [0])
        UVM_ERROR @   3228196 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc359cb [110000110101100111001011] vs 0x0 [0])
        UVM_ERROR @   3320196 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3a2d05 [1110100010110100000101] vs 0x0 [0])
        UVM_ERROR @   3341196 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x39fdb2 [1110011111110110110010] vs 0x0 [0])
        UVM_ERROR @   3359196 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbe9de8 [101111101001110111101000] vs 0x0 [0])