SPI_HOST Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.117m	16.709ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	26.788us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	54.733us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	401.500us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	51.307us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	43.969us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	54.733us	20	20	100.00
		spi_host_csr_aliasing	5.000s	51.307us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	15.228us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	17.116us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	5.000s	64.138us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	48.000s	3.759ms	50	50	100.00
		spi_host_error_cmd	5.000s	19.300us	50	50	100.00
		spi_host_event	11.833m	87.091ms	50	50	100.00
V2	clock_rate	spi_host_speed	11.000s	364.338us	50	50	100.00
V2	speed	spi_host_speed	11.000s	364.338us	50	50	100.00
V2	chip_select_timing	spi_host_speed	11.000s	364.338us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	5.067m	16.261ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	118.077us	50	50	100.00
V2	cpol_cpha	spi_host_speed	11.000s	364.338us	50	50	100.00
V2	full_cycle	spi_host_speed	11.000s	364.338us	50	50	100.00
V2	duplex	spi_host_smoke	2.117m	16.709ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.117m	16.709ms	50	50	100.00
V2	stress_all	spi_host_stress_all	13.367m	1.000s	49	50	98.00
V2	spien	spi_host_spien	46.000s	4.605ms	50	50	100.00
V2	stall	spi_host_status_stall	38.183m	1.000s	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	9.000s	1.588ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	48.000s	3.759ms	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	25.972us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	27.523us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	67.511us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	67.511us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	26.788us	5	5	100.00
		spi_host_csr_rw	4.000s	54.733us	20	20	100.00
		spi_host_csr_aliasing	5.000s	51.307us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	37.981us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	26.788us	5	5	100.00
		spi_host_csr_rw	4.000s	54.733us	20	20	100.00
		spi_host_csr_aliasing	5.000s	51.307us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	37.981us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	98.772us	20	20	100.00
		spi_host_sec_cm	5.000s	79.458us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	98.772us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	13.917m	91.917ms	10	10	100.00
		TOTAL			836	840	99.52

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.19	96.78	93.27	98.69	94.26	73.07	100.00	97.29	90.42

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test spi_host_status_stall has 2 failures.
  - 5.spi_host_status_stall.1821227810704006051917210938289972553869398326943393575784912023231371523203
    Line 1506, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 36.spi_host_status_stall.65143233120453857205875693934050504894224925796495569223746909761306434799059
    Line 2069, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/36.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 13.spi_host_stress_all.22032272395111073724300110704656722018299823162061353916999607441328011518937
    Line 140, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

3.spi_host_status_stall.61208966407104046195995606622731709895182423710149561676018589295477469196521
Line 775, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 1961303409 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 1961303409 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=1961303000 ps
  UVM_INFO @ 1961303409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---