SRAM_CTRL/MAIN Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.800m	1.162ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.100s	60.197us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.170s	11.270us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.380s	44.345us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.190s	21.851us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.520s	2.141ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.170s	11.270us	20	20	100.00
		sram_ctrl_csr_aliasing	2.190s	21.851us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.183m	21.548ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.938m	8.757ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	25.063m	33.579ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.117m	50.318ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	34.848m	31.811ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.886m	83.026ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.186m	55.567ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.556m	114.520ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.389m	1.935ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.499m	220.516ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.634m	779.055us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.838m	800.734us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.882m	3.662ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	21.854m	66.914ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.550s	1.611ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.907h	1.380s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.190s	23.629us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.310s	274.560us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.310s	274.560us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.100s	60.197us	5	5	100.00
		sram_ctrl_csr_rw	2.170s	11.270us	20	20	100.00
		sram_ctrl_csr_aliasing	2.190s	21.851us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.300s	29.182us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.100s	60.197us	5	5	100.00
		sram_ctrl_csr_rw	2.170s	11.270us	20	20	100.00
		sram_ctrl_csr_aliasing	2.190s	21.851us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.300s	29.182us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.297m	87.989ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.860s	3.226us	0	5	0.00
		sram_ctrl_tl_intg_err	4.500s	1.683ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.860s	3.226us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.500s	1.683ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	21.854m	66.914ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	21.854m	66.914ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.170s	11.270us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.556m	114.520ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.556m	114.520ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.556m	114.520ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.186m	55.567ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.680s	7.368ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.297m	87.989ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.860s	7.319ms	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.800m	1.162ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.800m	1.162ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.556m	114.520ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.860s	3.226us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.186m	55.567ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.860s	3.226us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.860s	3.226us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.800m	1.162ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.860s	3.226us	0	5	0.00
V2S		TOTAL			123	145	84.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.578m	2.822ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1168	1190	98.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	99.11	93.01	85.46	100.00	98.03	98.61	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:

  • Test sram_ctrl_readback_err has 11 failures.

    • 3.sram_ctrl_readback_err.18110204151101212457067550835119999758250867094992327868252217476701294437537
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1933847291 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x21) != exp (0x13)
        UVM_INFO @ 1933847291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.sram_ctrl_readback_err.61577110397850172480305180741721622255428326757185996588787713382565960823968
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/10.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2434689056 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3d) != exp (0x7c)
        UVM_INFO @ 2434689056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• Offending 'reqfifo_rvalid' has 6 failures:

  • Test sram_ctrl_mubi_enc_err has 6 failures.

    • 9.sram_ctrl_mubi_enc_err.32254592272243201623994303790144310843304530406069682049836384490647054356724
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1323352476 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1323352476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.sram_ctrl_mubi_enc_err.62596504791602921744819320630799695493488785243360941702500793796462517272528
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 4383673440 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 4383673440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 1.sram_ctrl_sec_cm.34107822833884468970194573680796133892856743933931221081337054842084952861853
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  38299256 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  38299256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.49618649239272349050534152676503679733648528537416513319632796876856675518151
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2090921 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2090921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 3.sram_ctrl_sec_cm.3075501897364905541249734770077485008857519415028221890574782967873807545432
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3225789 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3225789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.30797148030245675632081110209637274691021867968029043470153386560916646007311
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2074349 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2074349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.94171483936384919704026103198432597329286796269442823854758810851329054258104
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   3605215 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   3605215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---