SRAM_CTRL/RET Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.718m	635.415us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.010s	54.892us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.020s	25.991us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.880s	289.444us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.050s	70.099us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.390s	60.136us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.020s	25.991us	20	20	100.00
		sram_ctrl_csr_aliasing	2.050s	70.099us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	16.730s	7.270ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.060s	840.761us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	27.309m	35.979ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.001m	4.727ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.580m	20.697ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.551m	7.258ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.730s	1.495ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.171m	35.934ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.791m	9.254ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.619m	305.159ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.756m	164.532us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.640m	154.836us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.683m	1.167ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	16.857m	33.398ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.290s	46.349us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.225h	59.834ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.120s	12.068us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.370s	41.956us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.370s	41.956us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.010s	54.892us	5	5	100.00
		sram_ctrl_csr_rw	2.020s	25.991us	20	20	100.00
		sram_ctrl_csr_aliasing	2.050s	70.099us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.220s	61.643us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.010s	54.892us	5	5	100.00
		sram_ctrl_csr_rw	2.020s	25.991us	20	20	100.00
		sram_ctrl_csr_aliasing	2.050s	70.099us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.220s	61.643us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.640s	783.588us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.260s	24.215us	0	5	0.00
		sram_ctrl_tl_intg_err	4.640s	727.084us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.260s	24.215us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.640s	727.084us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	16.857m	33.398ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	16.857m	33.398ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.020s	25.991us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.171m	35.934ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.171m	35.934ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.171m	35.934ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.730s	1.495ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.610s	139.947us	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.640s	783.588us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.670s	240.323us	38	50	76.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.718m	635.415us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.718m	635.415us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.171m	35.934ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.260s	24.215us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.730s	1.495ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.260s	24.215us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.260s	24.215us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.718m	635.415us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.260s	24.215us	0	5	0.00
V2S		TOTAL			122	145	84.14
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.987m	11.083ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1166	1190	97.98

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	99.07	93.01	85.37	100.00	97.99	98.60	98.52

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 12 failures:

  • Test sram_ctrl_readback_err has 12 failures.

    • 1.sram_ctrl_readback_err.1142479820574498831490199757365030546472529084931363169663929167455326543061
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  23722081 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x43) != exp (0x1e)
        UVM_INFO @  23722081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.sram_ctrl_readback_err.110196312895180833606770012896615383142900588356273436473139844155607245073339
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  95394244 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6e) != exp (0x3d)
        UVM_INFO @  95394244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 10 more failures.

• Offending 'reqfifo_rvalid' has 6 failures:

  • Test sram_ctrl_mubi_enc_err has 6 failures.

    • 4.sram_ctrl_mubi_enc_err.78777155704758505025270249910320157299717443403889178205759427097940702230285
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  36596322 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  36596322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 19.sram_ctrl_mubi_enc_err.95578248125457704759380899261086871347717292674053278511869767046672640719270
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  22570232 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  22570232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 1.sram_ctrl_sec_cm.27781610525345283825699290465997641746567525439125150849474100966595231188998
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  25329700 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  25329700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.56878997808877064084280588500562344650912715156352317410368191634169158675422
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3550868 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3550868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.10741593024709606809504781459854358539529946068994643239986484109933395057015
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  24215048 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  24215048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.88068391845288144663121598502509040522332319902986148706855337000847168087010
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   8697926 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   8697926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 3.sram_ctrl_stress_all_with_rand_reset.62055339834537677971226016099931661048619413582462274300562633115197150868325
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 855755032 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 855755032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.75351334571230094916464983079080426559614346626686978179106341768864096520357
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   3078935 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   3078935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---