UART Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	36.440s	11.573ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.280s	15.150us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.260s	43.041us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	4.290s	261.550us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.320s	124.307us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.830s	53.059us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.260s	43.041us	20	20	100.00
		uart_csr_aliasing	2.320s	124.307us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.503m	126.160ms	50	50	100.00
V2	parity	uart_smoke	36.440s	11.573ms	50	50	100.00
		uart_tx_rx	5.503m	126.160ms	50	50	100.00
V2	parity_error	uart_intr	5.558m	188.260ms	50	50	100.00
		uart_rx_parity_err	5.292m	210.604ms	49	50	98.00
V2	watermark	uart_tx_rx	5.503m	126.160ms	50	50	100.00
		uart_intr	5.558m	188.260ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.652m	163.261ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.834m	92.071ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	13.051m	157.562ms	298	300	99.33
V2	rx_frame_err	uart_intr	5.558m	188.260ms	50	50	100.00
V2	rx_break_err	uart_intr	5.558m	188.260ms	50	50	100.00
V2	rx_timeout	uart_intr	5.558m	188.260ms	50	50	100.00
V2	perf	uart_perf	24.907m	35.028ms	50	50	100.00
V2	sys_loopback	uart_loopback	23.670s	7.861ms	50	50	100.00
V2	line_loopback	uart_loopback	23.670s	7.861ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.486m	124.822ms	4	50	8.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.133m	35.726ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	37.650s	12.245ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.040m	5.916ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	14.728m	243.853ms	50	50	100.00
V2	stress_all	uart_stress_all	26.558m	272.208ms	35	50	70.00
V2	alert_test	uart_alert_test	2.240s	38.152us	50	50	100.00
V2	intr_test	uart_intr_test	2.310s	14.111us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.720s	456.507us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.720s	456.507us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.280s	15.150us	5	5	100.00
		uart_csr_rw	2.260s	43.041us	20	20	100.00
		uart_csr_aliasing	2.320s	124.307us	5	5	100.00
		uart_same_csr_outstanding	2.360s	24.101us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.280s	15.150us	5	5	100.00
		uart_csr_rw	2.260s	43.041us	20	20	100.00
		uart_csr_aliasing	2.320s	124.307us	5	5	100.00
		uart_same_csr_outstanding	2.360s	24.101us	20	20	100.00
V2		TOTAL			1026	1090	94.13
V2S	tl_intg_err	uart_sec_cm	2.360s	38.825us	5	5	100.00
		uart_tl_intg_err	2.980s	287.125us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.980s	287.125us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.873m	4.902ms	89	100	89.00
V3		TOTAL			89	100	89.00
		TOTAL			1245	1320	94.32

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.01	99.48	98.25	74.67	--	98.14	100.00	99.53

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 31 failures:

  • Test uart_noise_filter has 21 failures.

    • 0.uart_noise_filter.36917617920239676491785780736075113595571198878289988021728795888278952132145
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 589610109 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 589610109 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 947990703 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 1959989691 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 1960323024 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (67 [0x43] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

    • 1.uart_noise_filter.78907029234051579848465002693969979505179966519153100701205980373428060088096
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log

        UVM_ERROR @   8591955 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  12716988 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  13550328 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  14300334 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  15050340 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 19 more failures.

  • Test uart_stress_all has 6 failures.

    • 4.uart_stress_all.105576066477142339898465880418043291999585191859382769268624772936734796149411
      Line 108, in log /nightly/runs/scratch/master/uart-sim-vcs/4.uart_stress_all/latest/run.log

        UVM_ERROR @ 326561254935 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 326561254935 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 326666569503 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 326677314687 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
        UVM_ERROR @ 326677353903 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
      

    • 19.uart_stress_all.85669894767430756170445604117979961989739217185376034845259136017000158852290
      Line 75, in log /nightly/runs/scratch/master/uart-sim-vcs/19.uart_stress_all/latest/run.log

        UVM_ERROR @ 64017810938 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 64043144246 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 64043144246 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 64165123922 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 64165123922 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
      

    • ... and 4 more failures.

  • Test uart_stress_all_with_rand_reset has 4 failures.

    • 26.uart_stress_all_with_rand_reset.91748321885436594685707340384471308900052533806069544324816451501988208995912
      Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 180702398 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 183202388 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 185535712 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 189035698 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 190202360 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • 58.uart_stress_all_with_rand_reset.29753217625992522664430208916997466001201798951961245004264253973970018029103
      Line 102, in log /nightly/runs/scratch/master/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3130306014 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3135340532 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3142444030 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3149582011 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3149754426 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 2 more failures.

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 29 failures:

  • Test uart_stress_all has 8 failures.

    • 3.uart_stress_all.39101747356135469099650743969974518233458175591159029883731352635863309090890
      Line 88, in log /nightly/runs/scratch/master/uart-sim-vcs/3.uart_stress_all/latest/run.log

        UVM_ERROR @ 299985109538 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 299985119538 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 299985129538 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (105 [0x69] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 300021369538 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 300021369538 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
      

    • 6.uart_stress_all.4183761511660701519103183047554958625800253284616792831196851828361643923896
      Line 93, in log /nightly/runs/scratch/master/uart-sim-vcs/6.uart_stress_all/latest/run.log

        UVM_ERROR @ 220770599179 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 9,                                 clk_pulses: 0
        UVM_ERROR @ 220770640846 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 220770682513 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 167 [0xa7]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 220913516989 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 220913516989 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 6 more failures.

  • Test uart_noise_filter has 17 failures.

    • 11.uart_noise_filter.56007296588665338047131230660875856267826660175496986783807720090562900836605
      Line 73, in log /nightly/runs/scratch/master/uart-sim-vcs/11.uart_noise_filter/latest/run.log

        UVM_ERROR @ 10947700825 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 10,                                 clk_pulses: 0
        UVM_ERROR @ 10947711134 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 10947721443 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (115 [0x73] vs 253 [0xfd]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 10947731752 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 10947742061 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (115 [0x73] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

    • 13.uart_noise_filter.68829535030255192706482857742763700757854557803120810077093402890968707405009
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/13.uart_noise_filter/latest/run.log

        UVM_ERROR @ 422790563 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 23,                                 clk_pulses: 0
        UVM_ERROR @ 422813290 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 422836017 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 422858744 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 422881471 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

    • ... and 15 more failures.

  • Test uart_stress_all_with_rand_reset has 4 failures.

    • 39.uart_stress_all_with_rand_reset.66837665767666277440235379758762443299701683663391025790974971627036126247728
      Line 74, in log /nightly/runs/scratch/master/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 122246137 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
        UVM_ERROR @ 122256663 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 122267189 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_INFO @ 190296727 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/635
        UVM_ERROR @ 217569593 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 13,                                 clk_pulses: 0
      

    • 56.uart_stress_all_with_rand_reset.66439338367218145819927636762724414181726427992766136891891851854145285480492
      Line 123, in log /nightly/runs/scratch/master/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5950103412 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 9,                                 clk_pulses: 0
        UVM_ERROR @ 5950145079 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 5950186746 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (18 [0x12] vs 242 [0xf2]) reg name: uart_reg_block.rdata
        UVM_INFO @ 6085687830 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/66
        UVM_ERROR @ 6199730409 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 12,                                 clk_pulses: 0
      

    • ... and 2 more failures.

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 9 failures:

  • Test uart_stress_all has 1 failures.

    • 1.uart_stress_all.37947242697089130298263232658830844990918464522212069845639932876725013551553
      Line 94, in log /nightly/runs/scratch/master/uart-sim-vcs/1.uart_stress_all/latest/run.log

        UVM_ERROR @ 153263566484 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 153263566484 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 153263566484 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 153297671742 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 7
        UVM_ERROR @ 153297682159 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
      

  • Test uart_stress_all_with_rand_reset has 2 failures.

    • 4.uart_stress_all_with_rand_reset.50888043426481718600801601727980663977149362043211177767890213140230456350112
      Line 79, in log /nightly/runs/scratch/master/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1518397188 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 1518397188 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1518397188 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_INFO @ 1707597188 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/900
        UVM_INFO @ 1908117188 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/900
      

    • 62.uart_stress_all_with_rand_reset.97458652514939467211690817919323280960643527002978701545749186251987845072758
      Line 186, in log /nightly/runs/scratch/master/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3727811705 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 3727811705 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3727811705 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_INFO @ 3751385376 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/324
        UVM_INFO @ 3789136584 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/324
      

  • Test uart_noise_filter has 6 failures.

    • 5.uart_noise_filter.87945437747341024082009189331865050813258653800188619275716819366505117503401
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/5.uart_noise_filter/latest/run.log

        UVM_ERROR @  58777302 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @  58777302 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  61527302 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @  61527302 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  71447302 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
      

    • 7.uart_noise_filter.109954296029380149599412072294472021604274291151451330010393779908650630043754
      Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/7.uart_noise_filter/latest/run.log

        UVM_ERROR @ 2914385942 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 2914385942 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2914385942 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 2924705942 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 9
        UVM_ERROR @ 2924745942 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
      

    • ... and 4 more failures.

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 3 failures:

  • Test uart_rx_parity_err has 1 failures.

    • 11.uart_rx_parity_err.48735099218396557630648346841075561965912776788379922440874227553005387822249
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/11.uart_rx_parity_err/latest/run.log

        UVM_ERROR @   1215758 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 768050723 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 1/9
        UVM_INFO @ 16997983637 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 2/9
        UVM_INFO @ 17613843297 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 3/9
        UVM_INFO @ 17704758368 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 4/9
      

  • Test uart_fifo_reset has 2 failures.

    • 142.uart_fifo_reset.106244757408720656706040909040358721600968652828630490182177254904687024260229
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/142.uart_fifo_reset/latest/run.log

        UVM_ERROR @  12931677 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 1641839139 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/9
        UVM_INFO @ 4516745355 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/9
        UVM_INFO @ 41888798892 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/9
        UVM_INFO @ 42882797898 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/9
      

    • 168.uart_fifo_reset.39317450526443695629100750650961125755324702042906923415466440149004199854884
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/168.uart_fifo_reset/latest/run.log

        UVM_ERROR @    944431 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 8294194411 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5
        UVM_INFO @ 8475692959 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/5
        UVM_INFO @ 13999812031 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/5
        UVM_INFO @ 14530358807 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/5
      

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 8.uart_noise_filter.38919708967172079822229612381705103643480428364451827598785632118580514498206
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log

        UVM_ERROR @  28490560 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @  31585860 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 167969540 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0
        UVM_ERROR @ 167993350 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 168017160 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 10.uart_noise_filter.32286908970400901444835699672405555592389384879553269798339110617047798652938
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/10.uart_noise_filter/latest/run.log

        UVM_ERROR @ 400502287 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 936048238 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 936089905 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 936214906 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 1301134492 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
      

• UVM_ERROR (cip_base_vseq.sv:832) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 67.uart_stress_all_with_rand_reset.73359439199449239987527741299319777857888588672517845305806951426754698073420
      Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @   6745853 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @   6745853 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @   6784814 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 1/5