CHIP Simulation Results

Friday June 20 2025 17:30:43 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.057m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.057m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	3.252m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	3.251m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.336m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.414m	6.451ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.414m	6.451ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.414m	6.451ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	46.980s	10.240us	0	3	0.00
		chip_sw_example_manufacturer	4.804m		0	3	0.00
		chip_sw_example_concurrency	4.805m	5.114ms	3	3	100.00
		chip_sw_uart_smoketest_signed	23.367s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	13.520s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	14.370s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	14.370s		0	3	0.00
V1	xbar_smoke	xbar_smoke	35.410s	65.912us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	3.667m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.167m	7.341ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	6.522m	5.001ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.759m		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.644m		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	3.110m		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.089m		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.940s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.940s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.621m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.628m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	4.197m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	4.197m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.642m	2.918ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	4.883m	4.625ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.566m	13.677ms	0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	18.572s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	18.114s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	15.468m	24.813ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	7.202m	6.745ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	33.526m	18.019ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	33.526m	18.019ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	26.480s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.125m	5.304ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.125m	5.304ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.052m	18.018ms	0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.494m	4.204ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.580m	5.856ms	3	3	100.00
		chip_sw_aes_idle	5.094m	3.397ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.658m	5.120ms	3	3	100.00
		chip_sw_kmac_idle	5.750m	5.202ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	18.826m	12.016ms	0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	21.673m	12.011ms	1	3	33.33
		chip_sw_clkmgr_off_kmac_trans	22.438m	12.015ms	1	3	33.33
		chip_sw_clkmgr_off_otbn_trans	19.925m	12.015ms	0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	17.842s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.752s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	17.211s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.164s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.470s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.449s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.106s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	17.842s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.752s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	17.211s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.164s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.470s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.449s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.106s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	19.504s		0	3	0.00
		chip_sw_aes_enc_jitter_en	52.330s	10.140us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	45.560s	10.240us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	58.730s	10.180us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	46.920s	10.260us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.033s		0	3	0.00
		chip_sw_clkmgr_jitter	4.830m	4.799ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.569m	5.189ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	19.629s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	44.570s	10.240us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	48.940s	10.240us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	57.320s	10.240us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	43.940s	10.320us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	50.090s	10.220us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	26.163s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.511s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	19.614s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	17.414s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	34.520m	17.150ms	92	100	92.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	12.905m	9.310ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	7.125m	5.304ms	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	18.567s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	12.905m	9.310ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	27.644s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	26.425s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	17.926s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	25.993s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	19.247s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	34.520m	17.150ms	92	100	92.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.566m	13.677ms	0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	35.940m	20.019ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.387m	9.050ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.160m	8.754ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.599m	4.587ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	34.520m	17.150ms	92	100	92.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	17.481s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	35.340s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	34.520m	17.150ms	92	100	92.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	19.549s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.160m	8.754ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	28.662s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	53.307s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	29.975s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.735s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	25.444s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	45.912s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	35.340s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	1.184m		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.032m		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	1.184m		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	1.184m		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	1.184m		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	9.048m	6.922ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.947m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	1.703m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	1.334m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.513m		0	3	0.00
		chip_sw_lc_ctrl_transition	1.184m		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	10.581m	10.263ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	13.200m	11.621ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	18.414s		0	3	0.00
		chip_prim_tl_access	25.189m	24.747ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	17.842s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.752s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	17.211s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.164s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.470s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.449s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.106s		0	3	0.00
		chip_rv_dm_lc_disabled	15.468m	24.813ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.779m	4.387ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	52.330s	10.140us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.560m	5.167ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.094m	3.397ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.564m	4.457ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	45.560s	10.240us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.658m	5.120ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.485m	4.932ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.303m	3.756ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	46.920s	10.260us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	10.581m	10.263ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	1.184m		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	48.690s	10.140us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	7.837m	6.005ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.750m	5.202ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	17.712s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	17.712s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	16.595s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	6.240m	5.755ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	31.986s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	10.581m	10.263ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	58.730s	10.180us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	22.490s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	19.504s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.580m	5.856ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.580m	5.856ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.580m	5.856ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	10.866m	5.994ms	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	13.200m	11.621ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	13.200m	11.621ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.579m	9.393ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.033s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.414s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	34.520m	17.150ms	92	100	92.00
		chip_sw_data_integrity_escalation	4.197m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	1.184m		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	10.866m	5.994ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	10.581m	10.263ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	12.579m	9.393ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.605m	4.250ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	10.866m	5.994ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	10.581m	10.263ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	12.579m	9.393ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.605m	4.250ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	1.184m		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	18.143s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.032m		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.947m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	1.703m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	1.334m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.513m		0	3	0.00
		chip_sw_lc_ctrl_transition	1.184m		0	15	0.00
		chip_prim_tl_access	25.189m	24.747ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	25.189m	24.747ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	56.247s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	51.833s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.511s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	19.504s		0	3	0.00
		chip_sw_aes_enc_jitter_en	52.330s	10.140us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	45.560s	10.240us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	58.730s	10.180us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	46.920s	10.260us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.033s		0	3	0.00
		chip_sw_clkmgr_jitter	4.830m	4.799ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	10.631m	7.036ms	3	3	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	10.631m	7.036ms	3	3	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	7.246m	5.883ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	5.584m	5.052ms	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.924m	5.220ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	11.581m	6.119ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.139m	5.957ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.108m	5.672ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	5.605m	4.250ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	35.940m	20.019ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	35.940m	20.019ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	6.503m	5.571ms	3	3	100.00
		chip_sw_aon_timer_smoketest	7.134m	5.921ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.918m	5.340ms	3	3	100.00
		chip_sw_csrng_smoketest	4.917m	4.472ms	3	3	100.00
		chip_sw_gpio_smoketest	5.703m	4.684ms	3	3	100.00
		chip_sw_hmac_smoketest	7.272m	5.424ms	3	3	100.00
		chip_sw_kmac_smoketest	6.976m	6.082ms	3	3	100.00
		chip_sw_otbn_smoketest	7.990m	4.579ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.249m	3.556ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.692m	5.690ms	3	3	100.00
		chip_sw_rv_timer_smoketest	8.977m	6.259ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.228m	4.889ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.338m	4.607ms	3	3	100.00
		chip_sw_uart_smoketest	6.408m	5.689ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	22.996s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	23.367s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.667m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	16.967s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.736m	4.870ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.295m	6.249ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	5.601m	6.063ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.375m	4.991ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.232s		0	3	0.00
		chip_rv_dm_lc_disabled	15.468m	24.813ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	27.770s		0	3	0.00
		chip_sw_lc_walkthrough_prod	17.707s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	37.181s		0	3	0.00
		chip_sw_lc_walkthrough_rma	15.023s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	21.232s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	29.792s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	38.479s		0	3	0.00
		rom_volatile_raw_unlock	16.264s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	18.792s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.629m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.407m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	4.931m	4.921ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	4.931m	4.921ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	14.370s		0	3	0.00
		chip_same_csr_outstanding	14.440s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	14.370s		0	3	0.00
		chip_same_csr_outstanding	14.440s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	5.060m	526.579us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	15.210s	12.875us	100	100	100.00
		xbar_smoke_large_delays	9.677m	2.605ms	100	100	100.00
		xbar_smoke_slow_rsp	10.415m	2.120ms	100	100	100.00
		xbar_random_zero_delays	2.236m	75.016us	100	100	100.00
		xbar_random_large_delays	36.673m	14.677ms	100	100	100.00
		xbar_random_slow_rsp	49.968m	14.324ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.850m	211.266us	100	100	100.00
		xbar_error_and_unmapped_addr	2.544m	228.905us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	4.195m	452.756us	100	100	100.00
		xbar_error_and_unmapped_addr	2.544m	228.905us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	8.223m	853.445us	100	100	100.00
		xbar_access_same_device_slow_rsp	58.573m	16.627ms	77	100	77.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.943m	473.162us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	33.792m	4.375ms	100	100	100.00
		xbar_stress_all_with_error	32.262m	4.495ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	57.696m	6.812ms	99	100	99.00
		xbar_stress_all_with_reset_error	57.383m	5.735ms	99	100	99.00
V2	rom_e2e_smoke	rom_e2e_smoke	16.275s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	18.344s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	18.817s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	16.100s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	14.550s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	16.206s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	16.664s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	14.944s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	15.964s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.573s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	15.905s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	14.742s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	18.580s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.100s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.757s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	19.179s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	14.286s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	18.437s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.361s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.804s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	18.027s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.668s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.811s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.840s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.233s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.117s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	22.512s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.687s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	18.545s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.333s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.296s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.215s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.625s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	17.734s		0	3	0.00
		rom_e2e_asm_init_dev	15.825s		0	3	0.00
		rom_e2e_asm_init_prod	17.374s		0	3	0.00
		rom_e2e_asm_init_prod_end	17.406s		0	3	0.00
		rom_e2e_asm_init_rma	18.742s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	18.801s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	18.877s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	18.437s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	18.287s		0	3	0.00
V2		TOTAL			1904	2429	78.39
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.359m	5.945ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	5.124m	3.554ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	14.652s		0	1	0.00
		rom_e2e_jtag_debug_dev	16.462s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.741s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	18.965s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	34.520m	17.150ms	92	100	92.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.396m		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	22.010m	15.311ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	17.877s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.779s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	14.652s		0	1	0.00
		rom_e2e_jtag_debug_dev	16.462s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.741s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	15.803s		0	1	0.00
		rom_e2e_jtag_inject_dev	15.799s		0	1	0.00
		rom_e2e_jtag_inject_rma	16.930s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.298m		0	3	0.00
V3		TOTAL			1	20	5.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	32.047m	14.879ms	3	3	100.00
		chip_plic_all_irqs_0	11.221m	6.309ms	3	3	100.00
		chip_plic_all_irqs_10	14.840m	7.007ms	3	3	100.00
		chip_sw_dma_inline_hashing	6.646m	4.886ms	3	3	100.00
		chip_sw_dma_abort	5.263m	4.314ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	17.755s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	17.408s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	18.472s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	18.364s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	17.373s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	17.135s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	19.415s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	17.377s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	16.945s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	17.096s		0	3	0.00
		chip_sw_mbx_smoketest	7.781m	5.791ms	3	3	100.00
		TOTAL			2032	2659	76.42

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
75.48	73.63	77.94	66.02	--	80.83	67.31	87.14

Failure Buckets

Job returned non-zero exit code has 455 failures:

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.7527600232530665427142478846872518817541535654899832256752614415694102524737
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (273ed1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 270.275s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_manufacturer.107549059120742062721768731080489952673957341778676230276022616416169319142620
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (48455f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 12.192s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_data_integrity_escalation has 6 failures.

0.chip_sw_data_integrity_escalation.85134420965478162762712258024203162275369021553941223474976032576517345294348
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (505655)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 236.257s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_data_integrity_escalation.52649981331262942774122219174795137112032368242172843533629901604673686935558
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (4efc20)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 24.796s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 4 more failures.

Test chip_sw_sleep_pin_wake has 3 failures.

0.chip_sw_sleep_pin_wake.95639406218302062662404178443732921433284374671763909498822664507417624421870
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (8d8925)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 260.896s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_wake.71591598403459312492321753348879197266121480737503556896030301419809887256954
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (4a811f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 52.903s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_sleep_pin_retention has 3 failures.

0.chip_sw_sleep_pin_retention.54995671047363145316759715009170016479636328208537017443012888625335550197718
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (51ef78)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 202.208s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_retention.98364248163825452693277483379782672940716427691557630148488818358473389781685
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (11f168)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 1.788s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_uart_tx_rx has 5 failures.

0.chip_sw_uart_tx_rx.4099568524183585334769935440986789546383417956829195266791990123982911708578
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (9ff2a1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 226.337s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_uart_tx_rx.26177282366904783350840787349273280881057663274762392862090620614604008592339
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (9dc392)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 14.803s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 3 more failures.

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:
- Test chip_sw_aes_enc_jitter_en has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en.93500571144056491594230070443265785342759779030600571725904678390849944751762
    Line 486, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en.112962888323052341704488791157776922765403120394649830129860028857047801720641
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_hmac_enc_jitter_en has 3 failures.
  - 0.chip_sw_hmac_enc_jitter_en.114412722631546254444103535659708135944943824060209087923085691679449827354920
    Line 438, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_enc_jitter_en.17043281161284472505120665385123147998127520729429221845618658287753889439620
    Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.99097634538166506399072731855100564878136786767814375027611883513908089974591
    Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.112263791041338831444641723177626874884258638949102210408934729392085879413917
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.44188398584453243814331408988981348388422330768253277851457403036656716934835
    Line 411, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_mode_kmac_jitter_en.105161149698304135559112121089495788617780277599416134246214108391642819650092
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.54271884875204053967175518461735403063093140432026473365012634298210784219210
    Line 452, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en_reduced_freq.69806081043227500695192731925959701466729834571492258007315657406722668876748
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 4 more tests.
Job timed out after * minutes has 25 failures:
- Test xbar_access_same_device_slow_rsp has 23 failures.
  - 4.xbar_access_same_device_slow_rsp.107110464114615207761582380576304107852520565352436216745306590988662153901558
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - 7.xbar_access_same_device_slow_rsp.44512021115320566781841838073939483269569779773543719896632241585954555587492
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 21 more failures.
- Test xbar_stress_all_with_reset_error has 1 failures.
  - 36.xbar_stress_all_with_reset_error.5864700239617153208866003725602019544611579676333967798363538308590558183314
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/36.xbar_stress_all_with_reset_error/latest/run.log
```
  Job timed out after 60 minutes
```
- Test xbar_stress_all_with_rand_reset has 1 failures.
  - 44.xbar_stress_all_with_rand_reset.114336973682418986086705796544238084975545056532306682499463830804319552264930
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/44.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 15 failures:
- Test chip_tl_errors has 15 failures.
  - 1.chip_tl_errors.72378984124601754893647358613719576294320836802910320820869905188815772053761
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5671.875068 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5671.875068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_tl_errors.50969729087496857865318314610346473944872856619110030795465172831805823798369
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5002.882644 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5002.882644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 11 failures:

Test chip_sw_rstmgr_cpu_info has 3 failures.

0.chip_sw_rstmgr_cpu_info.70337006012646536804727591781714576368499320504499943212396457084798298422762
Line 572, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20024.209942 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20024.209942 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_cpu_info.10967622894894426969644629896565623937566273877655033955033033366429661847476
Line 457, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20019.064054 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20019.064054 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_irq has 3 failures.

0.chip_sw_aon_timer_irq.75356443592597705069856757764339686813478853878701153375943570428366741677759
Line 576, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18021.559194 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18021.559194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_irq.13717166927699320023833199284696293090698021870245471202855024786779681740414
Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.924862 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.924862 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 5 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.5256786464994495973821531511918502285823560798048960080001174972261869478724
Line 566, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18016.842798 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.842798 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_sleep_wdog_sleep_pause.22248486754469176254192573293863486719206515133420700060482505627227453180009
Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18017.752358 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.752358 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 10 failures:

Test chip_sw_clkmgr_off_aes_trans has 3 failures.

0.chip_sw_clkmgr_off_aes_trans.62149935148889214417115734392452938753278809287552175985347527187033979948466
Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12020.308533 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12020.308533 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_aes_trans.29808860380784972995172491418273967705180508681960943868095496318603537669390
Line 450, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12015.334650 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.334650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_clkmgr_off_hmac_trans has 2 failures.

0.chip_sw_clkmgr_off_hmac_trans.27092225394306843601588315295379870126414354772486340784292452582448015920986
Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12019.122659 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12019.122659 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_hmac_trans.60598535809936897890378338257554604056365298039130539970192943006229832247280
Line 450, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12016.343495 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.343495 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 2 failures.

0.chip_sw_clkmgr_off_kmac_trans.104571432055819104537690103313795747678975494798787198982278550899105964924334
Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12014.560285 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.560285 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_kmac_trans.39102312142595277489784754213326688150233565585364346344458878462308732474161
Line 445, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12016.533262 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.533262 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 3 failures.

0.chip_sw_clkmgr_off_otbn_trans.13719980368982539375820766045841387579836068856028826548636271920965461451527
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12014.953688 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.953688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_otbn_trans.8239111966764259702194089769875323229720932085577455442596370129151450362896
Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12015.139958 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.139958 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
- Test chip_padctrl_attributes has 10 failures.
  - 0.chip_padctrl_attributes.82479681231223521880752440114292231297623234025908111629082823831158670185660
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 96
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.chip_padctrl_attributes.22942627198046964178630631023198054269417409823183297691564983009168619622216
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 96
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.95103049808251169462861713266012265359174779471190032739315421786623473684843
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.25062043001132620671066253233406396803552789766650533934467481374091294208106
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.78485498205943496168830191877686336803067751265805570879335453536600708212694
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.110903973497700195615223247890581463083291170189247259484305550561484067882360
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.64204332894074294567130007760154336864156986266224475798208960138484176278259
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.34942019163800560926643877279272643522499884094457780232612142411231578940615
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 6 failures:

Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation.102111603016041502688076603400451640126539836351157587175756876227107929115441
Line 491, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8926.839000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (32376958597396384020938141142324531530041392556073131903236096082943434689185 [0x4794b58bb33ccdf563de89a8d2cb15599e81567513bf9006bb37471ab1f60aa1] vs 53033791980112351140246476063008135836486541116848976712066473678623222475928 [0x7540100211b08525fefacd0db5abb313220256ae99c401b51f7635345fa72c98])
  UVM_INFO @ 8926.839000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation.102075463152096830749554783731270869577514932168407094834071069852751866717783
Line 474, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 10263.379880 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (50753993508767038016559004674491041584903212033374931135849962537850285942937 [0x7035be08f259b9299d9062006f5d106550bd9514e94dca400490a24f752d6899] vs 41073861334174922403863133815543395163208435065396446371244733327108827111143 [0x5acefb4eee9a17f0129c65f1c3998d11e9a89da58a794b2db48241498cfddee7])
  UVM_INFO @ 10263.379880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.26301841254789404871569836305414890747665420901951800313698195976669479884829
Line 508, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6415.277032 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (109215565466224623642890097218283732533828032978204989441099425204243692029110 [0xf175d1c7c80011e4c025d6570605cc95eb668203d6f2a3ec10d22f50588c84b6] vs 114159929791202220398654564930763038627777950312190532658059850003691287310995 [0xfc643b016f8aff74dd1f9bad3fa0f0ece135ea85db08bd40b286c6891c3f7293])
  UVM_INFO @ 6415.277032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation_prod.44331868019951959476008089572563687445624824230889610038990306604905991217859
Line 489, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7724.563216 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (98647488103290415516821081537565635547972428743421749456088541081233667066005 [0xda187fe839d3f39a9d19d62c58683c6da01a8fd8b40a32c8c11e43fb53bb0895] vs 1950065457850315696948934379219708751806541362941200471771709823848659038007 [0x44fb2abe7af0baf95d8496b03eed7a8b29aeab0b60472b956e00bec5af82f37])
  UVM_INFO @ 7724.563216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

Test chip_jtag_csr_rw has 3 failures.

0.chip_jtag_csr_rw.25052872530436360093695260952282380085601619587481475917859692633931647155690
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3102.026313 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'hb5458d0c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h0  a_user: 'h2690e  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3102.026313 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_csr_rw.19656896407711302991553148015185149538182678062004429263870564602949613272362
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5091.189870 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'ha7ec4b06  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h0  a_user: 'h2692f  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5091.189870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_jtag_mem_access has 3 failures.

0.chip_jtag_mem_access.64800487393227250464537257747198203927128243457161652714546688971647023026170
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3464.554240 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'haaeb2714  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h1  a_user: 'h248a3  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3464.554240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_mem_access.111059552601452960856109582459150009190346164076308417781027039232147581548794
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4624.510900 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h1678d162  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h1  a_user: 'h248de  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4624.510900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_example_rom has 3 failures.
  - 0.chip_sw_example_rom.28090101052821366102077845515018006260856024070469987395030956069159421321297
    Line 879, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_example_rom.12261055089929940858847798275067789431898505102817206971946372196876425062180
    Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.103950425300360510300443612489626032832381257510327904561011269559595957985335
    Line 598, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5365.771808 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5365.771808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.46324736979231945873089055001566693323301950180598506872518119905844066193718
    Line 458, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4451.098442 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4451.098442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 3 failures:
- Test chip_sw_rstmgr_alert_info has 3 failures.
  - 0.chip_sw_rstmgr_alert_info.84207531349036232819852537137683661457023581392480549493394291884643807853021
    Line 759, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 7153.743350 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 7153.743350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rstmgr_alert_info.89396150430754450066032872940232349455172357768246742000946232126815846093138
    Line 676, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8109.042620 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8109.042620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

Test chip_sw_soc_proxy_external_alerts has 3 failures.

0.chip_sw_soc_proxy_external_alerts.14540330456734445016678399437475268855684924198357295448698780670821028064180
Line 520, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 5133.511872 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5133.511872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_soc_proxy_external_alerts.105521607525249900478134724298404515653091524182927260003332331849361130988344
Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 5883.193730 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5883.193730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
- Test chip_sw_soc_proxy_external_wakeup has 3 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.108861427914979616905532386322723875316600189753490182243292280069380617103931
    Line 574, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3154.455490 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3154.455490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_soc_proxy_external_wakeup.32263059661533261743325078617458371911192742283354137246388951562179917982451
    Line 451, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5490.673852 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5490.673852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.23835822655143753391198799937662064693330684251231134605105595348991967548406
    Line 600, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4378.796072 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4378.796072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aon_timer_wdog_bite_reset.6024357801215371039573836392952668705311770227884617159854647851582062869098
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5303.925468 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5303.925468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.20561331854220465928157220369532839135413957194777953409178237486509074371467
    Line 540, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4707.569678 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4707.569678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.14647938942873770331951781399434322982744557078514874398274943264491755570873
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5628.129264 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5628.129264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_kmac_app_rom has 3 failures.
  - 0.chip_sw_kmac_app_rom.27968559483738990838955453259040179229280660769918493012124504519089182169055
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_app_rom.20579714558341606326223695729539127450538509947055775101400045104243241094934
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 3 failures:
- Test chip_rv_dm_ndm_reset_req has 3 failures.
  - 0.chip_rv_dm_ndm_reset_req.66615008038667624724640536312530120987253108605899272501679396548644157624367
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13807.128170 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13807.128170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_rv_dm_ndm_reset_req.41420931951828846388418810234320536895623844889661669783008984000459479139961
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13872.020176 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13872.020176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

Test chip_sw_dma_abort has 3 failures.

0.chip_sw_dma_abort.101783972239395401302115464629370207139908552918567210306070396210970156981662
Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4313.666328 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4313.666328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_dma_abort.20573047461510845246929277842823470642097216528512560181924309699154792346450
Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 5891.920304 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5891.920304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 56.chip_sw_all_escalation_resets.50236729843761687678505734949778740123415855001016970687486820163935656354901
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 4444.730672 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 4444.730672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 84.chip_sw_all_escalation_resets.85187888492240557689484078589508139884466922954349744061483112248264414099787
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 4907.002012 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 4907.002012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:

Test chip_sw_all_escalation_resets has 2 failures.

1.chip_sw_all_escalation_resets.29836096006663665770400106032876155912464394655324024999764929657459876199821
Line 497, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 12010.140001 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.chip_sw_all_escalation_resets.106574922788482072721502195374710499414295398139749846706800105735236607940153
Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 12010.300001 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 54.chip_sw_all_escalation_resets.95374373942195977707338335513014870558078882858257637986717188656152237857656
    Line 408, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.280001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 91.chip_sw_all_escalation_resets.68123096071451820124595919766230294138747394165248262061737576905453658630809
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.280001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36580) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures: