751b8fb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 3.000s | 99.925us | 0 | 1 | 0.00 |
| V1 | smoke | aes_smoke | 7.000s | 718.573us | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | aes_csr_hw_reset | 4.000s | 59.066us | 5 | 5 | 100.00 |
| V1 | csr_rw | aes_csr_rw | 6.000s | 431.415us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aes_csr_bit_bash | 4.000s | 76.870us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aes_csr_aliasing | 4.000s | 255.134us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 4.000s | 342.840us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 6.000s | 431.415us | 20 | 20 | 100.00 |
| aes_csr_aliasing | 4.000s | 255.134us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 55 | 106 | 51.89 | |||
| V2 | algorithm | aes_smoke | 7.000s | 718.573us | 0 | 50 | 0.00 |
| aes_config_error | 5.000s | 169.642us | 0 | 50 | 0.00 | ||
| aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 | ||
| V2 | key_length | aes_smoke | 7.000s | 718.573us | 0 | 50 | 0.00 |
| aes_config_error | 5.000s | 169.642us | 0 | 50 | 0.00 | ||
| aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 | ||
| V2 | back2back | aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 |
| aes_b2b | 6.000s | 361.382us | 0 | 50 | 0.00 | ||
| V2 | backpressure | aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 |
| V2 | multi_message | aes_smoke | 7.000s | 718.573us | 0 | 50 | 0.00 |
| aes_config_error | 5.000s | 169.642us | 0 | 50 | 0.00 | ||
| aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 | ||
| aes_alert_reset | 5.000s | 80.754us | 0 | 50 | 0.00 | ||
| V2 | failure_test | aes_man_cfg_err | 6.000s | 790.802us | 0 | 50 | 0.00 |
| aes_config_error | 5.000s | 169.642us | 0 | 50 | 0.00 | ||
| aes_alert_reset | 5.000s | 80.754us | 0 | 50 | 0.00 | ||
| V2 | trigger_clear_test | aes_clear | 5.000s | 147.215us | 0 | 50 | 0.00 |
| V2 | nist_test_vectors | aes_nist_vectors | 3.000s | 144.079us | 0 | 1 | 0.00 |
| V2 | reset_recovery | aes_alert_reset | 5.000s | 80.754us | 0 | 50 | 0.00 |
| V2 | stress | aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 |
| V2 | sideload | aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 |
| aes_sideload | 5.000s | 342.661us | 0 | 50 | 0.00 | ||
| V2 | deinitialization | aes_deinit | 10.000s | 600.192us | 0 | 50 | 0.00 |
| V2 | stress_all | aes_stress_all | 6.000s | 697.309us | 0 | 10 | 0.00 |
| V2 | alert_test | aes_alert_test | 7.000s | 480.772us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 5.000s | 546.274us | 0 | 20 | 0.00 |
| V2 | tl_d_illegal_access | aes_tl_errors | 5.000s | 546.274us | 0 | 20 | 0.00 |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 4.000s | 59.066us | 5 | 5 | 100.00 |
| aes_csr_rw | 6.000s | 431.415us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 4.000s | 255.134us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 4.000s | 64.030us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 4.000s | 59.066us | 5 | 5 | 100.00 |
| aes_csr_rw | 6.000s | 431.415us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 4.000s | 255.134us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 4.000s | 64.030us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 70 | 501 | 13.97 | |||
| V2S | reseeding | aes_reseed | 5.000s | 342.090us | 0 | 50 | 0.00 |
| V2S | fault_inject | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| aes_control_fi | 11.000s | 811.529us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 12.000s | 770.283us | 0 | 350 | 0.00 | ||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 4.000s | 108.684us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 4.000s | 108.684us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 4.000s | 108.684us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 4.000s | 108.684us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 5.000s | 559.459us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | aes_sec_cm | 5.000s | 657.881us | 5 | 5 | 100.00 |
| aes_tl_intg_err | 4.000s | 350.323us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 4.000s | 350.323us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 5.000s | 80.754us | 0 | 50 | 0.00 |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 4.000s | 108.684us | 20 | 20 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 7.000s | 718.573us | 0 | 50 | 0.00 |
| aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 | ||
| aes_alert_reset | 5.000s | 80.754us | 0 | 50 | 0.00 | ||
| aes_core_fi | 6.000s | 309.246us | 0 | 70 | 0.00 | ||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 4.000s | 108.684us | 20 | 20 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 9.000s | 624.142us | 0 | 50 | 0.00 |
| aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sideload | aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 |
| aes_sideload | 5.000s | 342.661us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 9.000s | 624.142us | 0 | 50 | 0.00 |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 9.000s | 624.142us | 0 | 50 | 0.00 |
| V2S | sec_cm_key_sec_wipe | aes_readability | 9.000s | 624.142us | 0 | 50 | 0.00 |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 9.000s | 624.142us | 0 | 50 | 0.00 |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 9.000s | 624.142us | 0 | 50 | 0.00 |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 |
| V2S | sec_cm_key_masking | aes_stress | 6.000s | 540.851us | 0 | 50 | 0.00 |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| V2S | sec_cm_main_fsm_redun | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| aes_control_fi | 11.000s | 811.529us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 12.000s | 770.283us | 0 | 350 | 0.00 | ||
| aes_ctr_fi | 5.000s | 146.966us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| aes_control_fi | 11.000s | 811.529us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 12.000s | 770.283us | 0 | 350 | 0.00 | ||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 12.000s | 770.283us | 0 | 350 | 0.00 |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| aes_control_fi | 11.000s | 811.529us | 0 | 300 | 0.00 | ||
| aes_ctr_fi | 5.000s | 146.966us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_sparse | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| aes_control_fi | 11.000s | 811.529us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 12.000s | 770.283us | 0 | 350 | 0.00 | ||
| aes_ctr_fi | 5.000s | 146.966us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 5.000s | 80.754us | 0 | 50 | 0.00 |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| aes_control_fi | 11.000s | 811.529us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 12.000s | 770.283us | 0 | 350 | 0.00 | ||
| aes_ctr_fi | 5.000s | 146.966us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| aes_control_fi | 11.000s | 811.529us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 12.000s | 770.283us | 0 | 350 | 0.00 | ||
| aes_ctr_fi | 5.000s | 146.966us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| aes_control_fi | 11.000s | 811.529us | 0 | 300 | 0.00 | ||
| aes_ctr_fi | 5.000s | 146.966us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 5.000s | 378.114us | 0 | 50 | 0.00 |
| aes_control_fi | 11.000s | 811.529us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 12.000s | 770.283us | 0 | 350 | 0.00 | ||
| V2S | TOTAL | 65 | 985 | 6.60 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 5.000s | 288.031us | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 190 | 1602 | 11.86 |
UVM_FATAL (aes_scoreboard.sv:714) scoreboard [scoreboard] has 1412 failures:
Test aes_wake_up has 1 failures.
0.aes_wake_up.101691949416478933400262509595329090253424039698609431510610893682457440433913
Line 1544, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_wake_up/latest/run.log
UVM_FATAL @ 99925364 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.36023865876455572648254026133288355381228240619062776719841508304525119761702
Line 1184, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_nist_vectors/latest/run.log
UVM_FATAL @ 144079461 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
Test aes_deinit has 50 failures.
0.aes_deinit.89915046512617223393256774121510734403703791665554016427060772275695899330649
Line 1176, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_deinit/latest/run.log
UVM_FATAL @ 347518137 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
1.aes_deinit.96360783002904068695902114336776573667538326502684075670614608335983399285270
Line 1058, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_deinit/latest/run.log
UVM_FATAL @ 101390086 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
... and 48 more failures.
Test aes_man_cfg_err has 50 failures.
0.aes_man_cfg_err.115503115715929718977914340121909419763959071452277019632084391527424218202723
Line 902, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
UVM_FATAL @ 90578700 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
1.aes_man_cfg_err.91951520514988115760006930281843400759176340170491237860438054112272326787039
Line 1630, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
UVM_FATAL @ 73373271 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
... and 48 more failures.
Test aes_readability has 50 failures.
0.aes_readability.33592675480839504931146697604408956900705210022385535803584394280874378331303
Line 3588, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_readability/latest/run.log
UVM_FATAL @ 203183499 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
1.aes_readability.52163210737105967080278095210069802305315504659899396692626811838770803341828
Line 1228, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_readability/latest/run.log
UVM_FATAL @ 204315968 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
... and 48 more failures.
... and 16 more tests.
Job returned non-zero exit code has 1 failures:
cov_merge
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_merge/merged/cov_merge.log
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
[make]: cov_merge
imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
*I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
Created log file /nightly/current_run/opentitan/startup.log
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
Job killed most likely because its dependent job failed. has 1 failures: