751b8fb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 9.000s | 84.079us | 0 | 1 | 0.00 |
| V1 | smoke | aes_smoke | 9.000s | 56.672us | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | aes_csr_hw_reset | 3.000s | 81.529us | 5 | 5 | 100.00 |
| V1 | csr_rw | aes_csr_rw | 4.000s | 71.588us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aes_csr_bit_bash | 3.000s | 55.530us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aes_csr_aliasing | 4.000s | 175.992us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 4.000s | 86.251us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 4.000s | 71.588us | 20 | 20 | 100.00 |
| aes_csr_aliasing | 4.000s | 175.992us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 55 | 106 | 51.89 | |||
| V2 | algorithm | aes_smoke | 9.000s | 56.672us | 0 | 50 | 0.00 |
| aes_config_error | 8.000s | 112.905us | 0 | 50 | 0.00 | ||
| aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 | ||
| V2 | key_length | aes_smoke | 9.000s | 56.672us | 0 | 50 | 0.00 |
| aes_config_error | 8.000s | 112.905us | 0 | 50 | 0.00 | ||
| aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 | ||
| V2 | back2back | aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 |
| aes_b2b | 9.000s | 73.490us | 0 | 50 | 0.00 | ||
| V2 | backpressure | aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 |
| V2 | multi_message | aes_smoke | 9.000s | 56.672us | 0 | 50 | 0.00 |
| aes_config_error | 8.000s | 112.905us | 0 | 50 | 0.00 | ||
| aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 | ||
| aes_alert_reset | 9.000s | 56.520us | 0 | 50 | 0.00 | ||
| V2 | failure_test | aes_man_cfg_err | 9.000s | 82.288us | 0 | 50 | 0.00 |
| aes_config_error | 8.000s | 112.905us | 0 | 50 | 0.00 | ||
| aes_alert_reset | 9.000s | 56.520us | 0 | 50 | 0.00 | ||
| V2 | trigger_clear_test | aes_clear | 9.000s | 97.159us | 0 | 50 | 0.00 |
| V2 | nist_test_vectors | aes_nist_vectors | 9.000s | 52.752us | 0 | 1 | 0.00 |
| V2 | reset_recovery | aes_alert_reset | 9.000s | 56.520us | 0 | 50 | 0.00 |
| V2 | stress | aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 |
| V2 | sideload | aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 |
| aes_sideload | 9.000s | 66.898us | 0 | 50 | 0.00 | ||
| V2 | deinitialization | aes_deinit | 9.000s | 135.992us | 0 | 50 | 0.00 |
| V2 | stress_all | aes_stress_all | 9.000s | 63.343us | 0 | 10 | 0.00 |
| V2 | alert_test | aes_alert_test | 9.000s | 54.707us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 4.000s | 68.700us | 0 | 20 | 0.00 |
| V2 | tl_d_illegal_access | aes_tl_errors | 4.000s | 68.700us | 0 | 20 | 0.00 |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 3.000s | 81.529us | 5 | 5 | 100.00 |
| aes_csr_rw | 4.000s | 71.588us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 4.000s | 175.992us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 4.000s | 154.057us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 3.000s | 81.529us | 5 | 5 | 100.00 |
| aes_csr_rw | 4.000s | 71.588us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 4.000s | 175.992us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 4.000s | 154.057us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 70 | 501 | 13.97 | |||
| V2S | reseeding | aes_reseed | 9.000s | 107.782us | 0 | 50 | 0.00 |
| V2S | fault_inject | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| aes_control_fi | 9.000s | 92.686us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 9.000s | 71.703us | 0 | 350 | 0.00 | ||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 4.000s | 53.686us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 4.000s | 53.686us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 4.000s | 53.686us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 4.000s | 53.686us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 4.000s | 76.799us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | aes_sec_cm | 9.000s | 146.269us | 5 | 5 | 100.00 |
| aes_tl_intg_err | 4.000s | 60.562us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 4.000s | 60.562us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 9.000s | 56.520us | 0 | 50 | 0.00 |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 4.000s | 53.686us | 20 | 20 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 9.000s | 56.672us | 0 | 50 | 0.00 |
| aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 | ||
| aes_alert_reset | 9.000s | 56.520us | 0 | 50 | 0.00 | ||
| aes_core_fi | 9.000s | 69.095us | 0 | 70 | 0.00 | ||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 4.000s | 53.686us | 20 | 20 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 9.000s | 248.853us | 0 | 50 | 0.00 |
| aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sideload | aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 |
| aes_sideload | 9.000s | 66.898us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 9.000s | 248.853us | 0 | 50 | 0.00 |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 9.000s | 248.853us | 0 | 50 | 0.00 |
| V2S | sec_cm_key_sec_wipe | aes_readability | 9.000s | 248.853us | 0 | 50 | 0.00 |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 9.000s | 248.853us | 0 | 50 | 0.00 |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 9.000s | 248.853us | 0 | 50 | 0.00 |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 |
| V2S | sec_cm_key_masking | aes_stress | 9.000s | 65.000us | 0 | 50 | 0.00 |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| V2S | sec_cm_main_fsm_redun | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| aes_control_fi | 9.000s | 92.686us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 9.000s | 71.703us | 0 | 350 | 0.00 | ||
| aes_ctr_fi | 9.000s | 63.471us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| aes_control_fi | 9.000s | 92.686us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 9.000s | 71.703us | 0 | 350 | 0.00 | ||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 9.000s | 71.703us | 0 | 350 | 0.00 |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| aes_control_fi | 9.000s | 92.686us | 0 | 300 | 0.00 | ||
| aes_ctr_fi | 9.000s | 63.471us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_sparse | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| aes_control_fi | 9.000s | 92.686us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 9.000s | 71.703us | 0 | 350 | 0.00 | ||
| aes_ctr_fi | 9.000s | 63.471us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 9.000s | 56.520us | 0 | 50 | 0.00 |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| aes_control_fi | 9.000s | 92.686us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 9.000s | 71.703us | 0 | 350 | 0.00 | ||
| aes_ctr_fi | 9.000s | 63.471us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| aes_control_fi | 9.000s | 92.686us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 9.000s | 71.703us | 0 | 350 | 0.00 | ||
| aes_ctr_fi | 9.000s | 63.471us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| aes_control_fi | 9.000s | 92.686us | 0 | 300 | 0.00 | ||
| aes_ctr_fi | 9.000s | 63.471us | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 9.000s | 74.395us | 0 | 50 | 0.00 |
| aes_control_fi | 9.000s | 92.686us | 0 | 300 | 0.00 | ||
| aes_cipher_fi | 9.000s | 71.703us | 0 | 350 | 0.00 | ||
| V2S | TOTAL | 65 | 985 | 6.60 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 9.000s | 83.635us | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 190 | 1602 | 11.86 |
UVM_FATAL (aes_scoreboard.sv:714) scoreboard [scoreboard] has 1412 failures:
Test aes_wake_up has 1 failures.
0.aes_wake_up.102984173215946097129282081737162127603648382843494093383682513579137110544062
Line 458, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_wake_up/latest/run.log
UVM_FATAL @ 84079139 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.68735811883651822865601708425999845364170241999992729169373443209282573580380
Line 530, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_nist_vectors/latest/run.log
UVM_FATAL @ 52751779 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
Test aes_deinit has 50 failures.
0.aes_deinit.71313956574370795269285540467421148323082269702674528126294289473163638566049
Line 452, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
UVM_FATAL @ 135991897 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
1.aes_deinit.1782074369862469866930646219254787884179066360868227915180228099423872001919
Line 478, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_deinit/latest/run.log
UVM_FATAL @ 113869385 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
... and 48 more failures.
Test aes_man_cfg_err has 50 failures.
0.aes_man_cfg_err.100982322707851675058352270656196744583606782760926821507074559273472973922819
Line 458, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
UVM_FATAL @ 82287979 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
1.aes_man_cfg_err.115749099121635823386080330069879208775102855162165787450800064361513145170581
Line 464, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
UVM_FATAL @ 83871463 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
... and 48 more failures.
Test aes_readability has 50 failures.
0.aes_readability.18293057408008086114022436400241793158584493315893334853003172241804737558609
Line 476, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
UVM_FATAL @ 248852981 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
1.aes_readability.60667158531741586157755524161154308817300691847880565875642163937438721377577
Line 1628, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_readability/latest/run.log
UVM_FATAL @ 74700178 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
... and 48 more failures.
... and 16 more tests.
Job returned non-zero exit code has 1 failures:
cov_merge
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_merge/merged/cov_merge.log
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
[make]: cov_merge
imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
*I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
Created log file /nightly/current_run/opentitan/startup.log
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
Job killed most likely because its dependent job failed. has 1 failures: